DMA Simulation Results

Friday September 19 2025 17:02:16 UTC

GitHub Revision: e60097d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 dma_memory_smoke dma_memory_smoke 50.000s 1 25 4.00
V1 dma_handshake_smoke dma_handshake_smoke 38.000s 1 25 4.00
V1 dma_generic_smoke dma_generic_smoke 46.000s 3 50 6.00
V1 csr_hw_reset dma_csr_hw_reset 38.000s 0 5 0.00
V1 csr_rw dma_csr_rw 47.000s 1 20 5.00
V1 csr_bit_bash dma_csr_bit_bash 38.000s 0 5 0.00
V1 csr_aliasing dma_csr_aliasing 38.000s 0 5 0.00
V1 csr_mem_rw_with_rand_reset dma_csr_mem_rw_with_rand_reset 39.000s 2 20 10.00
V1 regwen_csr_and_corresponding_lockable_csr dma_csr_rw 47.000s 1 20 5.00
dma_csr_aliasing 38.000s 0 5 0.00
V1 TOTAL 8 155 5.16
V2 dma_memory_region_lock dma_memory_region_lock 54.000s 0 5 0.00
V2 dma_memory_tl_error dma_memory_stress 34.000s 0 3 0.00
V2 dma_handshake_tl_error dma_handshake_stress 46.000s 0 3 0.00
V2 dma_handshake_stress dma_handshake_stress 46.000s 0 3 0.00
V2 dma_memory_stress dma_memory_stress 34.000s 0 3 0.00
V2 dma_generic_stress dma_generic_stress 34.000s 0 5 0.00
V2 dma_handshake_mem_buffer_overflow dma_handshake_stress 46.000s 0 3 0.00
V2 dma_abort dma_abort 37.000s 0 5 0.00
V2 dma_stress_all dma_stress_all 1.183m 8.525ms 1 3 33.33
V2 alert_test dma_alert_test 46.000s 2 50 4.00
V2 intr_test dma_intr_test 46.000s 0 50 0.00
V2 tl_d_oob_addr_access dma_tl_errors 46.000s 1 20 5.00
V2 tl_d_illegal_access dma_tl_errors 46.000s 1 20 5.00
V2 tl_d_outstanding_access dma_csr_hw_reset 38.000s 0 5 0.00
dma_csr_rw 47.000s 1 20 5.00
dma_csr_aliasing 38.000s 0 5 0.00
dma_same_csr_outstanding 38.000s 2 20 10.00
V2 tl_d_partial_access dma_csr_hw_reset 38.000s 0 5 0.00
dma_csr_rw 47.000s 1 20 5.00
dma_csr_aliasing 38.000s 0 5 0.00
dma_same_csr_outstanding 38.000s 2 20 10.00
V2 TOTAL 6 164 3.66
V2S dma_illegal_addr_range dma_mem_enabled 34.000s 0 5 0.00
dma_generic_stress 34.000s 0 5 0.00
dma_handshake_stress 46.000s 0 3 0.00
V2S dma_config_lock dma_config_lock 37.000s 0 15 0.00
V2S tl_intg_err dma_tl_intg_err 34.000s 2 20 10.00
dma_sec_cm 38.000s 0 5 0.00
V2S TOTAL 2 45 4.44
Unmapped tests dma_short_transfer 1.017m 26.579ms 1 25 4.00
dma_longer_transfer 46.000s 0 5 0.00
dma_stress_all_with_rand_reset 29.000s 0 1 0.00
TOTAL 17 395 4.30

Failure Buckets