e60097d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 41.241s | 40 | 50 | 80.00 | |
| V1 | csr_hw_reset | edn_csr_hw_reset | 15.899s | 4 | 5 | 80.00 | |
| V1 | csr_rw | edn_csr_rw | 18.238s | 18 | 20 | 90.00 | |
| V1 | csr_bit_bash | edn_csr_bit_bash | 3.910s | 579.066us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | edn_csr_aliasing | 24.037s | 4 | 5 | 80.00 | |
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 28.171s | 18 | 20 | 90.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 18.238s | 18 | 20 | 90.00 | |
| edn_csr_aliasing | 24.037s | 4 | 5 | 80.00 | |||
| V1 | TOTAL | 89 | 105 | 84.76 | |||
| V2 | firmware | edn_genbits | 46.230s | 2.220ms | 267 | 300 | 89.00 |
| V2 | csrng_commands | edn_genbits | 46.230s | 2.220ms | 267 | 300 | 89.00 |
| V2 | genbits | edn_genbits | 46.230s | 2.220ms | 267 | 300 | 89.00 |
| V2 | interrupts | edn_intr | 22.315s | 46 | 50 | 92.00 | |
| V2 | alerts | edn_alert | 32.709s | 180 | 200 | 90.00 | |
| V2 | errs | edn_err | 30.633s | 86 | 100 | 86.00 | |
| V2 | disable | edn_disable | 28.715s | 44 | 50 | 88.00 | |
| edn_disable_auto_req_mode | 30.356s | 42 | 50 | 84.00 | |||
| V2 | stress_all | edn_stress_all | 28.694s | 42 | 50 | 84.00 | |
| V2 | intr_test | edn_intr_test | 26.500s | 49 | 50 | 98.00 | |
| V2 | alert_test | edn_alert_test | 22.344s | 45 | 50 | 90.00 | |
| V2 | tl_d_oob_addr_access | edn_tl_errors | 17.908s | 18 | 20 | 90.00 | |
| V2 | tl_d_illegal_access | edn_tl_errors | 17.908s | 18 | 20 | 90.00 | |
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 15.899s | 4 | 5 | 80.00 | |
| edn_csr_rw | 18.238s | 18 | 20 | 90.00 | |||
| edn_csr_aliasing | 24.037s | 4 | 5 | 80.00 | |||
| edn_same_csr_outstanding | 30.945s | 18 | 20 | 90.00 | |||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 15.899s | 4 | 5 | 80.00 | |
| edn_csr_rw | 18.238s | 18 | 20 | 90.00 | |||
| edn_csr_aliasing | 24.037s | 4 | 5 | 80.00 | |||
| edn_same_csr_outstanding | 30.945s | 18 | 20 | 90.00 | |||
| V2 | TOTAL | 837 | 940 | 89.04 | |||
| V2S | tl_intg_err | edn_sec_cm | 8.350s | 4.506ms | 5 | 5 | 100.00 |
| edn_tl_intg_err | 4.910s | 435.981us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | edn_regwen | 0.820s | 20.831us | 10 | 10 | 100.00 |
| V2S | sec_cm_config_mubi | edn_alert | 32.709s | 180 | 200 | 90.00 | |
| V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 8.350s | 4.506ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 8.350s | 4.506ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fifo_ctr_redun | edn_sec_cm | 8.350s | 4.506ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | edn_sec_cm | 8.350s | 4.506ms | 5 | 5 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 32.709s | 180 | 200 | 90.00 | |
| edn_sec_cm | 8.350s | 4.506ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 32.709s | 180 | 200 | 90.00 | |
| V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 4.910s | 435.981us | 20 | 20 | 100.00 |
| V2S | TOTAL | 35 | 35 | 100.00 | |||
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 2.812h | 10.000s | 18 | 50 | 36.00 |
| V3 | TOTAL | 18 | 50 | 36.00 | |||
| TOTAL | 979 | 1130 | 86.64 |
Job returned non-zero exit code has 113 failures:
Test edn_stress_all has 6 failures.
0.edn_stress_all.114314533659223383701295939305133574001856668141638494867913543863650922401727
Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_stress_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 20:28 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
1.edn_stress_all.58711164172455878487518782125391782952039316601587315159264835897196401095770
Log /nightly/current_run/scratch/master/edn-sim-vcs/1.edn_stress_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 20:28 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 4 more failures.
Test edn_stress_all_with_rand_reset has 6 failures.
0.edn_stress_all_with_rand_reset.105783907225905417849048426986944690959103424349287702456268588407701371766222
Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 20:28 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
6.edn_stress_all_with_rand_reset.52744519300191763456295270151061050812072509757021244394753282052900860559536
Log /nightly/current_run/scratch/master/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 20:29 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 4 more failures.
Test edn_csr_aliasing has 1 failures.
0.edn_csr_aliasing.30723505290021636880729562604455108940668297278220440060290621502387273560575
Log /nightly/current_run/scratch/master/edn-sim-vcs/0.edn_csr_aliasing/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 17:36 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test edn_intr_test has 1 failures.
1.edn_intr_test.43206121710401181062375002411762188185827283698114565434955673235779850218527
Log /nightly/current_run/scratch/master/edn-sim-vcs/1.edn_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 17:36 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test edn_disable_auto_req_mode has 7 failures.
2.edn_disable_auto_req_mode.78557189726012036363311184080668905621267352019475853930774523775739340488902
Log /nightly/current_run/scratch/master/edn-sim-vcs/2.edn_disable_auto_req_mode/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 20:29 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
18.edn_disable_auto_req_mode.73529537876961847441451571650061350287797070357405657466097699926771973246194
Log /nightly/current_run/scratch/master/edn-sim-vcs/18.edn_disable_auto_req_mode/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 20:31 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 5 more failures.
... and 13 more tests.
Job timed out after * minutes has 38 failures:
Test edn_stress_all_with_rand_reset has 25 failures.
1.edn_stress_all_with_rand_reset.10786859535663554107169254923767284519901388193174000271136033819165692795792
Log /nightly/current_run/scratch/master/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log
Job timed out after 180 minutes
4.edn_stress_all_with_rand_reset.83036773364979060665917605076405147602590890691549500338581730293815606487325
Log /nightly/current_run/scratch/master/edn-sim-vcs/4.edn_stress_all_with_rand_reset/latest/run.log
Job timed out after 180 minutes
... and 23 more failures.
Test edn_same_csr_outstanding has 1 failures.
12.edn_same_csr_outstanding.49074488097553297520373532923217200175744710720322992356208533641013844783037
Log /nightly/current_run/scratch/master/edn-sim-vcs/12.edn_same_csr_outstanding/latest/run.log
Job timed out after 60 minutes
Test edn_alert has 2 failures.
19.edn_alert.61912869314246414731634709295931342101043203418479328416349842287599763166376
Log /nightly/current_run/scratch/master/edn-sim-vcs/19.edn_alert/latest/run.log
Job timed out after 60 minutes
51.edn_alert.19043370905436543891672386318793036245910554444454152091400194739337506697561
Log /nightly/current_run/scratch/master/edn-sim-vcs/51.edn_alert/latest/run.log
Job timed out after 60 minutes
Test edn_genbits has 3 failures.
23.edn_genbits.46905198877576272072226726872775593535185581024023727212707591932923681170962
Log /nightly/current_run/scratch/master/edn-sim-vcs/23.edn_genbits/latest/run.log
Job timed out after 60 minutes
42.edn_genbits.44124103997575767415027089579358340560051375425715107355414743497849297115016
Log /nightly/current_run/scratch/master/edn-sim-vcs/42.edn_genbits/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
Test edn_intr has 1 failures.
27.edn_intr.112345848818508382540242412741467278876422609670238356149849740757299523743234
Log /nightly/current_run/scratch/master/edn-sim-vcs/27.edn_intr/latest/run.log
Job timed out after 60 minutes
... and 4 more tests.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
40.edn_stress_all_with_rand_reset.96830011526100449480399471521728102593895996815906881598867224235913321506257
Line 365, in log /nightly/current_run/scratch/master/edn-sim-vcs/40.edn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed most likely because its dependent job failed. has 1 failures: