e60097d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 10.380s | 11.073ms | 10 | 10 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0.820s | 29.061us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.850s | 34.862us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 10.690s | 6.967ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 4.300s | 3.375ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 24.007m | 942.839ms | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.850s | 34.862us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 4.300s | 3.375ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 64 | 65 | 98.46 | |||
| V2 | long_msg | hmac_long_msg | 54.800s | 5.635ms | 9 | 10 | 90.00 |
| V2 | back_pressure | hmac_back_pressure | 1.116m | 6.711ms | 20 | 25 | 80.00 |
| V2 | test_vectors | hmac_test_sha256_vectors | 3.402m | 7.090ms | 29 | 30 | 96.67 |
| hmac_test_sha384_vectors | 7.077m | 13.386ms | 67 | 75 | 89.33 | ||
| hmac_test_sha512_vectors | 7.477m | 56.499ms | 66 | 75 | 88.00 | ||
| hmac_test_hmac256_vectors | 21.972s | 46 | 50 | 92.00 | |||
| hmac_test_hmac384_vectors | 32.598s | 53 | 60 | 88.33 | |||
| hmac_test_hmac512_vectors | 26.684s | 62 | 75 | 82.67 | |||
| V2 | burst_wr | hmac_burst_wr | 27.360s | 2.899ms | 45 | 50 | 90.00 |
| V2 | datapath_stress | hmac_datapath_stress | 18.284m | 51.119ms | 9 | 10 | 90.00 |
| V2 | error | hmac_error | 1.155m | 8.186ms | 9 | 10 | 90.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.434m | 6.377ms | 10 | 10 | 100.00 |
| V2 | save_and_restore | hmac_smoke | 10.380s | 11.073ms | 10 | 10 | 100.00 |
| hmac_long_msg | 54.800s | 5.635ms | 9 | 10 | 90.00 | ||
| hmac_back_pressure | 1.116m | 6.711ms | 20 | 25 | 80.00 | ||
| hmac_datapath_stress | 18.284m | 51.119ms | 9 | 10 | 90.00 | ||
| hmac_burst_wr | 27.360s | 2.899ms | 45 | 50 | 90.00 | ||
| hmac_stress_all | 30.675m | 18.858ms | 47 | 50 | 94.00 | ||
| V2 | fifo_empty_status_interrupt | hmac_smoke | 10.380s | 11.073ms | 10 | 10 | 100.00 |
| hmac_long_msg | 54.800s | 5.635ms | 9 | 10 | 90.00 | ||
| hmac_back_pressure | 1.116m | 6.711ms | 20 | 25 | 80.00 | ||
| hmac_datapath_stress | 18.284m | 51.119ms | 9 | 10 | 90.00 | ||
| hmac_wipe_secret | 1.434m | 6.377ms | 10 | 10 | 100.00 | ||
| hmac_test_sha256_vectors | 3.402m | 7.090ms | 29 | 30 | 96.67 | ||
| hmac_test_sha384_vectors | 7.077m | 13.386ms | 67 | 75 | 89.33 | ||
| hmac_test_sha512_vectors | 7.477m | 56.499ms | 66 | 75 | 88.00 | ||
| hmac_test_hmac256_vectors | 21.972s | 46 | 50 | 92.00 | |||
| hmac_test_hmac384_vectors | 32.598s | 53 | 60 | 88.33 | |||
| hmac_test_hmac512_vectors | 26.684s | 62 | 75 | 82.67 | |||
| V2 | wide_digest_configurable_key_length | hmac_smoke | 10.380s | 11.073ms | 10 | 10 | 100.00 |
| hmac_long_msg | 54.800s | 5.635ms | 9 | 10 | 90.00 | ||
| hmac_back_pressure | 1.116m | 6.711ms | 20 | 25 | 80.00 | ||
| hmac_datapath_stress | 18.284m | 51.119ms | 9 | 10 | 90.00 | ||
| hmac_burst_wr | 27.360s | 2.899ms | 45 | 50 | 90.00 | ||
| hmac_error | 1.155m | 8.186ms | 9 | 10 | 90.00 | ||
| hmac_wipe_secret | 1.434m | 6.377ms | 10 | 10 | 100.00 | ||
| hmac_test_sha256_vectors | 3.402m | 7.090ms | 29 | 30 | 96.67 | ||
| hmac_test_sha384_vectors | 7.077m | 13.386ms | 67 | 75 | 89.33 | ||
| hmac_test_sha512_vectors | 7.477m | 56.499ms | 66 | 75 | 88.00 | ||
| hmac_test_hmac256_vectors | 21.972s | 46 | 50 | 92.00 | |||
| hmac_test_hmac384_vectors | 32.598s | 53 | 60 | 88.33 | |||
| hmac_test_hmac512_vectors | 26.684s | 62 | 75 | 82.67 | |||
| hmac_stress_all | 30.675m | 18.858ms | 47 | 50 | 94.00 | ||
| V2 | stress_all | hmac_stress_all | 30.675m | 18.858ms | 47 | 50 | 94.00 |
| V2 | alert_test | hmac_alert_test | 28.850s | 46 | 50 | 92.00 | |
| V2 | intr_test | hmac_intr_test | 32.004s | 45 | 50 | 90.00 | |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 13.994s | 19 | 20 | 95.00 | |
| V2 | tl_d_illegal_access | hmac_tl_errors | 13.994s | 19 | 20 | 95.00 | |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0.820s | 29.061us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.850s | 34.862us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 4.300s | 3.375ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 16.562s | 19 | 20 | 95.00 | |||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0.820s | 29.061us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.850s | 34.862us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 4.300s | 3.375ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 16.562s | 19 | 20 | 95.00 | |||
| V2 | TOTAL | 601 | 670 | 89.70 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0.910s | 106.197us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 3.060s | 385.616us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 3.060s | 385.616us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 10.380s | 11.073ms | 10 | 10 | 100.00 |
| V3 | stress_reset | hmac_stress_reset | 22.228s | 22 | 25 | 88.00 | |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 4.409m | 7.174ms | 30 | 35 | 85.71 |
| V3 | TOTAL | 52 | 60 | 86.67 | |||
| Unmapped tests | hmac_directed | 1.800s | 227.008us | 1 | 1 | 100.00 | |
| TOTAL | 743 | 821 | 90.50 |
Job returned non-zero exit code has 68 failures:
Test hmac_stress_all_with_rand_reset has 5 failures.
0.hmac_stress_all_with_rand_reset.57696336022761929761089758052536149205596353794233910715188905921535509565946
Log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 17:05 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
16.hmac_stress_all_with_rand_reset.99558491972957059687022158256395299070707211105618027366035718086870609266343
Log /nightly/current_run/scratch/master/hmac-sim-vcs/16.hmac_stress_all_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 17:08 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 3 more failures.
Test hmac_intr_test has 5 failures.
0.hmac_intr_test.66449257169621419543320212649681261726748162982562191271147166871654713395607
Log /nightly/current_run/scratch/master/hmac-sim-vcs/0.hmac_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 17:22 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
7.hmac_intr_test.68717346267766418120788120697969399458203547050937273063029457864518921586721
Log /nightly/current_run/scratch/master/hmac-sim-vcs/7.hmac_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 17:23 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 3 more failures.
Test hmac_test_sha384_vectors has 5 failures.
2.hmac_test_sha384_vectors.100195471025487258010559452145594398966434670078799010868525876477338745919537
Log /nightly/current_run/scratch/master/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 17:05 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
22.hmac_test_sha384_vectors.46451431627304286223128120410925691909710586491128462953559534815898612107511
Log /nightly/current_run/scratch/master/hmac-sim-vcs/22.hmac_test_sha384_vectors/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 17:10 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 3 more failures.
Test hmac_long_msg has 1 failures.
3.hmac_long_msg.68205148622548801547017775187424408329432279960203455734840195004168111475987
Log /nightly/current_run/scratch/master/hmac-sim-vcs/3.hmac_long_msg/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 17:05 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test hmac_back_pressure has 5 failures.
3.hmac_back_pressure.39446537712405715785018958013688291734609344058996379927332076644320962077227
Log /nightly/current_run/scratch/master/hmac-sim-vcs/3.hmac_back_pressure/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 17:05 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
14.hmac_back_pressure.22778691548419599575579198610304238617012753408520628101627017792122323584658
Log /nightly/current_run/scratch/master/hmac-sim-vcs/14.hmac_back_pressure/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 17:08 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 3 more failures.
... and 15 more tests.
Job timed out after * minutes has 11 failures:
Test hmac_burst_wr has 1 failures.
8.hmac_burst_wr.25487609638309175695220615781848526077705372117392322603483739873789135669154
Log /nightly/current_run/scratch/master/hmac-sim-vcs/8.hmac_burst_wr/latest/run.log
Job timed out after 60 minutes
Test hmac_test_sha384_vectors has 3 failures.
8.hmac_test_sha384_vectors.86117874690004794763777785147108048370398527568106802695293782949955568798389
Log /nightly/current_run/scratch/master/hmac-sim-vcs/8.hmac_test_sha384_vectors/latest/run.log
Job timed out after 60 minutes
32.hmac_test_sha384_vectors.8384061516133889918391926358261853689564987090106403365470044400384367912612
Log /nightly/current_run/scratch/master/hmac-sim-vcs/32.hmac_test_sha384_vectors/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
Test hmac_test_sha512_vectors has 3 failures.
25.hmac_test_sha512_vectors.362345840405817869973279170825411593302569463018481488822341267712036034249
Log /nightly/current_run/scratch/master/hmac-sim-vcs/25.hmac_test_sha512_vectors/latest/run.log
Job timed out after 60 minutes
34.hmac_test_sha512_vectors.47131438160189563997924658279026173574619016541752910998564761380238581007970
Log /nightly/current_run/scratch/master/hmac-sim-vcs/34.hmac_test_sha512_vectors/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
Test hmac_test_hmac384_vectors has 2 failures.
27.hmac_test_hmac384_vectors.45000488018761379624265875837366328268468953534479975887354872897852205797879
Log /nightly/current_run/scratch/master/hmac-sim-vcs/27.hmac_test_hmac384_vectors/latest/run.log
Job timed out after 60 minutes
44.hmac_test_hmac384_vectors.39522699394028334100153653943177140992232825857591750836170035776985666222565
Log /nightly/current_run/scratch/master/hmac-sim-vcs/44.hmac_test_hmac384_vectors/latest/run.log
Job timed out after 60 minutes
Test hmac_test_hmac512_vectors has 1 failures.
31.hmac_test_hmac512_vectors.42302459229957583913396529811862601407790013854692584886386321863758423026091
Log /nightly/current_run/scratch/master/hmac-sim-vcs/31.hmac_test_hmac512_vectors/latest/run.log
Job timed out after 60 minutes
... and 1 more tests.