e60097d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.042m | 1.998ms | 47 | 50 | 94.00 |
| V1 | target_smoke | i2c_target_smoke | 32.655s | 43 | 50 | 86.00 | |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.690s | 26.678us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 18.273s | 19 | 20 | 95.00 | |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 3.530s | 532.891us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.400s | 93.275us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 28.469s | 19 | 20 | 95.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 18.273s | 19 | 20 | 95.00 | |
| i2c_csr_aliasing | 1.400s | 93.275us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 143 | 155 | 92.26 | |||
| V2 | host_error_intr | i2c_host_error_intr | 21.974s | 4 | 50 | 8.00 | |
| V2 | host_stress_all | i2c_host_stress_all | 32.434m | 96.672ms | 5 | 50 | 10.00 |
| V2 | host_maxperf | i2c_host_perf | 36.980m | 27.682ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 22.582s | 46 | 50 | 92.00 | |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 3.550m | 5.125ms | 47 | 50 | 94.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 1.729m | 47.702ms | 45 | 50 | 90.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 26.462s | 44 | 50 | 88.00 | |
| i2c_host_fifo_fmt_empty | 20.190s | 48 | 50 | 96.00 | |||
| i2c_host_fifo_reset_rx | 26.408s | 41 | 50 | 82.00 | |||
| V2 | host_fifo_full | i2c_host_fifo_full | 2.528m | 12.773ms | 46 | 50 | 92.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 29.520s | 4.070ms | 44 | 50 | 88.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 26.849s | 13 | 50 | 26.00 | |
| V2 | target_glitch | i2c_target_glitch | 1.830s | 526.987us | 0 | 2 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 17.819m | 64.582ms | 41 | 50 | 82.00 |
| V2 | target_maxperf | i2c_target_perf | 26.717s | 44 | 50 | 88.00 | |
| V2 | target_fifo_empty | i2c_target_stress_rd | 54.620s | 7.410ms | 47 | 50 | 94.00 |
| i2c_target_intr_smoke | 19.952s | 46 | 50 | 92.00 | |||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 18.469s | 46 | 50 | 92.00 | |
| i2c_target_fifo_reset_tx | 28.587s | 45 | 50 | 90.00 | |||
| V2 | target_fifo_full | i2c_target_stress_wr | 15.514m | 62.789ms | 47 | 50 | 94.00 |
| i2c_target_stress_rd | 54.620s | 7.410ms | 47 | 50 | 94.00 | ||
| i2c_target_intr_stress_wr | 4.774m | 24.193ms | 41 | 50 | 82.00 | ||
| V2 | target_timeout | i2c_target_timeout | 28.706s | 47 | 50 | 94.00 | |
| V2 | target_clock_stretch | i2c_target_stretch | 57.320s | 5.966ms | 40 | 50 | 80.00 |
| V2 | bad_address | i2c_target_bad_addr | 24.760s | 43 | 50 | 86.00 | |
| V2 | target_mode_glitch | i2c_target_hrst | 26.468s | 29 | 50 | 58.00 | |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 19.810s | 46 | 50 | 92.00 | |
| i2c_target_fifo_watermarks_tx | 18.315s | 46 | 50 | 92.00 | |||
| V2 | host_mode_config_perf | i2c_host_perf | 36.980m | 27.682ms | 48 | 50 | 96.00 |
| i2c_host_perf_precise | 9.062m | 24.286ms | 47 | 50 | 94.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 29.520s | 4.070ms | 44 | 50 | 88.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 24.529s | 42 | 50 | 84.00 | |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 28.089s | 45 | 50 | 90.00 | |
| i2c_target_nack_acqfull_addr | 31.026s | 43 | 50 | 86.00 | |||
| i2c_target_nack_txstretch | 29.006s | 29 | 50 | 58.00 | |||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 24.523s | 44 | 50 | 88.00 | |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 24.134s | 44 | 50 | 88.00 | |
| V2 | alert_test | i2c_alert_test | 28.358s | 46 | 50 | 92.00 | |
| V2 | intr_test | i2c_intr_test | 22.309s | 48 | 50 | 96.00 | |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 24.347s | 18 | 20 | 90.00 | |
| V2 | tl_d_illegal_access | i2c_tl_errors | 24.347s | 18 | 20 | 90.00 | |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.690s | 26.678us | 5 | 5 | 100.00 |
| i2c_csr_rw | 18.273s | 19 | 20 | 95.00 | |||
| i2c_csr_aliasing | 1.400s | 93.275us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 0.950s | 721.929us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.690s | 26.678us | 5 | 5 | 100.00 |
| i2c_csr_rw | 18.273s | 19 | 20 | 95.00 | |||
| i2c_csr_aliasing | 1.400s | 93.275us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 0.950s | 721.929us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1465 | 1792 | 81.75 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 22.517s | 18 | 20 | 90.00 | |
| i2c_sec_cm | 0.830s | 71.103us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 22.517s | 18 | 20 | 90.00 | |
| V2S | TOTAL | 23 | 25 | 92.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 13.910s | 3.775ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 28.896s | 0 | 50 | 0.00 | |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 31.950s | 10.326ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1631 | 2042 | 79.87 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 84.14 | 97.31 | 89.29 | 74.17 | 48.21 | 93.97 | 96.41 | 89.64 |
Job returned non-zero exit code has 168 failures:
Test i2c_alert_test has 4 failures.
0.i2c_alert_test.6722302658867371972247223536907258559940371039538673663406157439747713862080
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_alert_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 01:39 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
28.i2c_alert_test.81523151213784400197966399063247162115405388723803868282520690645617665541938
Log /nightly/current_run/scratch/master/i2c-sim-vcs/28.i2c_alert_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 01:55 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 2 more failures.
Test i2c_csr_mem_rw_with_rand_reset has 1 failures.
0.i2c_csr_mem_rw_with_rand_reset.100969747048964765242339786522586012352383998963068656772151712584788829334923
Log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_csr_mem_rw_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 17:59 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test i2c_target_intr_stress_wr has 8 failures.
1.i2c_target_intr_stress_wr.72076712809907862370895826978487130780322485652691906840987432876504483136948
Log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_intr_stress_wr/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 01:39 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
11.i2c_target_intr_stress_wr.34129830459401610385892053716076888366254688961746575689659991526636061587975
Log /nightly/current_run/scratch/master/i2c-sim-vcs/11.i2c_target_intr_stress_wr/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 01:44 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 6 more failures.
Test i2c_target_smbus_maxlen has 6 failures.
1.i2c_target_smbus_maxlen.87445153019013405800325023117660709777833336507320102782994364622566422508349
Log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_smbus_maxlen/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 01:39 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
21.i2c_target_smbus_maxlen.39628261059057171416895700572039537670250430220057185012328314735201923447654
Log /nightly/current_run/scratch/master/i2c-sim-vcs/21.i2c_target_smbus_maxlen/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 01:50 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 4 more failures.
Test i2c_target_nack_acqfull_addr has 7 failures.
1.i2c_target_nack_acqfull_addr.100949286083447825928350737721798608307095369725398487374364226880149783914639
Log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_nack_acqfull_addr/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 01:39 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
3.i2c_target_nack_acqfull_addr.106594812805325442075044153785056397199708395468930633872211354446192759053336
Log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_nack_acqfull_addr/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 01:40 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 5 more failures.
... and 38 more tests.
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 86 failures:
0.i2c_host_error_intr.110304444639303566259200125143962020054636410700076484891350149440414517075174
Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 31893841 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 31893841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_error_intr.10125121751875880615363351745832440178028073053989075144032608500892799817129
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 40614126 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 40614126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 40 more failures.
0.i2c_host_stress_all.1169915970388381309607755907667085490042376509805532123264543725673707494880
Line 95, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 32474292 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 32474292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_stress_all.31141265385491306146350550543949282850788683953745106354993619341564112427891
Line 110, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 12852967408 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 12852967408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
1.i2c_host_mode_toggle.85237163048828479315803696951408010019660228850036331699858195392231211606868
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 52743972 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 52743972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_mode_toggle.7930187711648771211610757137796299265474974778999657254016454470346602488092
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 14208152 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 14208152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
5.i2c_target_stress_all_with_rand_reset.88877423761259110307457776207163298466147754025561312003185641615175496710349
Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3653228555 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 3653228555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.25781033810298937298274945534993052754360117751045167270793010636382783879098
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 32516530 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 32516530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 23 failures:
2.i2c_target_unexp_stop.99126827746913295031755533699283482148761289426176417732271144034497616605798
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 346955826 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 107 [0x6b])
UVM_INFO @ 346955826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.53710924939448126760598553576919157443742410456888488933122278576080326983144
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 21176163 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 134 [0x86])
UVM_INFO @ 21176163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
Job timed out after * minutes has 19 failures:
Test i2c_host_may_nack has 1 failures.
9.i2c_host_may_nack.669396813153648741077333389294896370109475576289227127198444103098248122598
Log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_host_may_nack/latest/run.log
Job timed out after 60 minutes
Test i2c_target_nack_txstretch has 1 failures.
12.i2c_target_nack_txstretch.94298862405918977524341019410914217964361759302102126930463920725194464210036
Log /nightly/current_run/scratch/master/i2c-sim-vcs/12.i2c_target_nack_txstretch/latest/run.log
Job timed out after 60 minutes
Test i2c_host_smoke has 1 failures.
15.i2c_host_smoke.33039075782610834033138616273901507160672450632459921243456952207376680173956
Log /nightly/current_run/scratch/master/i2c-sim-vcs/15.i2c_host_smoke/latest/run.log
Job timed out after 60 minutes
Test i2c_target_stretch has 1 failures.
16.i2c_target_stretch.9081662605463837229458422863656642311868738195558367791880423553244831931456
Log /nightly/current_run/scratch/master/i2c-sim-vcs/16.i2c_target_stretch/latest/run.log
Job timed out after 60 minutes
Test i2c_host_stress_all has 5 failures.
19.i2c_host_stress_all.31603930418914517145822971464507685654669566249440117688229325617724148163711
Log /nightly/current_run/scratch/master/i2c-sim-vcs/19.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
26.i2c_host_stress_all.21911510406272698504422459948661364635259296265794628362868600350563619175100
Log /nightly/current_run/scratch/master/i2c-sim-vcs/26.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
... and 3 more failures.
... and 10 more tests.
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 17 failures:
1.i2c_host_stress_all.107974454943559700107702002756758977350860243060433870306005655206107850457242
Line 141, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 66007488194 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4760505
4.i2c_host_stress_all.75967341635891620764429117889422106767317259280706710993276720473811038916014
Line 139, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 164880217435 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4471299
... and 5 more failures.
6.i2c_host_mode_toggle.34000017086169442754581220508288741777074799159254283132962322446876301978389
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 65267852 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @10900
9.i2c_host_mode_toggle.9777031970773402850887430264022164496587025629478405416025654503386037970071
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 141446540 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @26872
... and 8 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 16 failures:
0.i2c_target_hrst.57165869787435140815641601829349372409536678242275435951364461854278718925463
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10236783757 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10236783757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_hrst.76272156654631758779280330241338262203556127057559260794589364181175128842003
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10166778443 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10166778443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (cip_base_vseq.sv:945) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
0.i2c_host_stress_all_with_rand_reset.30246550964789441557284730352513431854345652748563537421638305977249092387215
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 352155910 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 352155910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.16561100026722313240398282849232629746331624824311420923300383677101236790471
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 857145800 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 857145800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.100514956626276860731633255103330834351718474436821690919564270020552857591933
Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2125599044 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2125599044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.65383244369543641826025553988447777107873590848365948302087826287420303144474
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3735492068 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3735492068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 15 failures:
1.i2c_target_unexp_stop.9393354638097966973409353478839831425333971627812464684123948794869775833410
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1336202990 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1336202990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.82437309094845439727923435975459605395375790634217229582554353016610109353047
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1142929722 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1142929722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 15 failures:
1.i2c_target_nack_txstretch.74051749946716500463029404292881057655707906220466467049555043975245619990258
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 146200063 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 146200063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_nack_txstretch.69796124864051847404767044051980295677425280124220965980782657651903701641615
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 197828153 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 197828153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 10 failures:
7.i2c_host_mode_toggle.67990471929712464592514301860278923242856668739329597841434535515121642616710
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 38761283 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
10.i2c_host_mode_toggle.93825695244901085128344677697190345467695651381516886317474325771162118663289
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 51592237 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 8 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 7 failures:
0.i2c_target_unexp_stop.28607532048776686255812738843409219962192123410393152670575619375435337634208
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 245478646 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 245478646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.87328785615907332636988771778743522227061610016500028662384778844571338791622
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 1099925143 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 1099925143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
7.i2c_target_stretch.110938171687651314913989751694641345103607040507030123832176776744885450133448
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10002266198 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10002266198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_target_stretch.45106483406093949912616113613063842684601399315118884982566770966606965860132
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/21.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10015766581 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10015766581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
Test i2c_target_fifo_watermarks_tx has 1 failures.
9.i2c_target_fifo_watermarks_tx.90398385224838939946602781588090882289672246002805912149738243460984749387636
Line 118, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_tx_stretch_ctrl has 2 failures.
10.i2c_target_tx_stretch_ctrl.39026143699821433610103140084732370247884338953623019549203364238453666798184
Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/10.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
23.i2c_target_tx_stretch_ctrl.41587222993550030185335371795991327051544103881773330949441216400976728150708
Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/23.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
15.i2c_host_mode_toggle.27255845874670660256267142753945943707407620067551531766375204809475002341371
Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/15.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 38351487 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x71080a94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 38351487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.i2c_host_mode_toggle.60992436325065592925526178385671161518223375942590543391840373167883329581899
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/27.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 171206968 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xe1927e14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 171206968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:
0.i2c_target_glitch.27487765971728450171420370541202883300429666568286077025987140617072980578332
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 1902675557 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 1902675557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_glitch.21942224367075332414563899989946121490444000494802945518930002856527273158223
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log
UVM_ERROR @ 526987380 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 526987380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:
12.i2c_host_stress_all.3933101037473476688294189634585209417627141635882973554692973658677945604021
Line 129, in log /nightly/current_run/scratch/master/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 17742046130 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @18138449
48.i2c_host_stress_all.19570390096127536730894190435105298365973908087029834416910287624186008690399
Line 151, in log /nightly/current_run/scratch/master/i2c-sim-vcs/48.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 40500126377 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3466491
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
Test i2c_target_stress_all has 1 failures.
34.i2c_target_stress_all.15058528436923486210053794909495449601522018284250388244194089706261886263114
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/34.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 46781326729 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 46781326729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_intr_stress_wr has 1 failures.
39.i2c_target_intr_stress_wr.79631233832844578011387529349544666065806696406944593490561547910120013240506
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/39.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 46591589383 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 46591589383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
44.i2c_target_bad_addr.68883574727985741665415236454085271201057998765644529334917166495972134451279
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/44.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.i2c_target_bad_addr.102995490145040791558551348396428121219828797371416492726058157939535988020626
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/48.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---