e60097d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | keymgr_smoke | 18.322s | 49 | 50 | 98.00 | |
| V1 | random | keymgr_random | 38.850s | 2.450ms | 48 | 50 | 96.00 |
| V1 | csr_hw_reset | keymgr_csr_hw_reset | 0.900s | 29.390us | 5 | 5 | 100.00 |
| V1 | csr_rw | keymgr_csr_rw | 29.827s | 19 | 20 | 95.00 | |
| V1 | csr_bit_bash | keymgr_csr_bit_bash | 9.950s | 858.962us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | keymgr_csr_aliasing | 7.030s | 514.817us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 1.690s | 272.147us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 29.827s | 19 | 20 | 95.00 | |
| keymgr_csr_aliasing | 7.030s | 514.817us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 151 | 155 | 97.42 | |||
| V2 | cfgen_during_op | keymgr_cfg_regwen | 52.540s | 6.589ms | 46 | 50 | 92.00 |
| V2 | sideload | keymgr_sideload | 20.515s | 48 | 50 | 96.00 | |
| keymgr_sideload_kmac | 33.650s | 7.562ms | 47 | 50 | 94.00 | ||
| keymgr_sideload_aes | 20.441s | 45 | 50 | 90.00 | |||
| keymgr_sideload_otbn | 44.420s | 5.996ms | 47 | 50 | 94.00 | ||
| V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 24.519s | 45 | 50 | 90.00 | |
| V2 | lc_disable | keymgr_lc_disable | 24.598s | 47 | 50 | 94.00 | |
| V2 | kmac_error_response | keymgr_kmac_rsp_err | 14.080s | 3.193ms | 50 | 50 | 100.00 |
| V2 | invalid_sw_input | keymgr_sw_invalid_input | 28.495s | 47 | 50 | 94.00 | |
| V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 32.563s | 45 | 50 | 90.00 | |
| V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 20.296s | 48 | 50 | 96.00 | |
| V2 | stress_all | keymgr_stress_all | 2.530m | 50.209ms | 48 | 50 | 96.00 |
| V2 | intr_test | keymgr_intr_test | 26.652s | 48 | 50 | 96.00 | |
| V2 | alert_test | keymgr_alert_test | 27.467s | 47 | 50 | 94.00 | |
| V2 | tl_d_oob_addr_access | keymgr_tl_errors | 3.310s | 558.883us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | keymgr_tl_errors | 3.310s | 558.883us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 0.900s | 29.390us | 5 | 5 | 100.00 |
| keymgr_csr_rw | 29.827s | 19 | 20 | 95.00 | |||
| keymgr_csr_aliasing | 7.030s | 514.817us | 5 | 5 | 100.00 | ||
| keymgr_same_csr_outstanding | 2.570s | 360.053us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | keymgr_csr_hw_reset | 0.900s | 29.390us | 5 | 5 | 100.00 |
| keymgr_csr_rw | 29.827s | 19 | 20 | 95.00 | |||
| keymgr_csr_aliasing | 7.030s | 514.817us | 5 | 5 | 100.00 | ||
| keymgr_same_csr_outstanding | 2.570s | 360.053us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 698 | 740 | 94.32 | |||
| V2S | sec_cm_additional_check | keymgr_sec_cm | 6.870s | 4.585ms | 5 | 5 | 100.00 |
| V2S | tl_intg_err | keymgr_sec_cm | 6.870s | 4.585ms | 5 | 5 | 100.00 |
| keymgr_tl_intg_err | 30.269s | 16 | 20 | 80.00 | |||
| V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 4.130s | 799.178us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 4.130s | 799.178us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 4.130s | 799.178us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 4.130s | 799.178us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 18.528s | 18 | 20 | 90.00 | |
| V2S | prim_count_check | keymgr_sec_cm | 6.870s | 4.585ms | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | keymgr_sec_cm | 6.870s | 4.585ms | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 30.269s | 16 | 20 | 80.00 | |
| V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 4.130s | 799.178us | 20 | 20 | 100.00 |
| V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 52.540s | 6.589ms | 46 | 50 | 92.00 |
| V2S | sec_cm_reseed_config_regwen | keymgr_random | 38.850s | 2.450ms | 48 | 50 | 96.00 |
| keymgr_csr_rw | 29.827s | 19 | 20 | 95.00 | |||
| V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 38.850s | 2.450ms | 48 | 50 | 96.00 |
| keymgr_csr_rw | 29.827s | 19 | 20 | 95.00 | |||
| V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 38.850s | 2.450ms | 48 | 50 | 96.00 |
| keymgr_csr_rw | 29.827s | 19 | 20 | 95.00 | |||
| V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 24.598s | 47 | 50 | 94.00 | |
| V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 32.563s | 45 | 50 | 90.00 | |
| V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 32.563s | 45 | 50 | 90.00 | |
| V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 38.850s | 2.450ms | 48 | 50 | 96.00 |
| V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 32.792s | 48 | 50 | 96.00 | |
| V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 6.870s | 4.585ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 6.870s | 4.585ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 6.870s | 4.585ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 26.160s | 6.500ms | 46 | 50 | 92.00 |
| V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 24.598s | 47 | 50 | 94.00 | |
| V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 6.870s | 4.585ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 6.870s | 4.585ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 6.870s | 4.585ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 26.160s | 6.500ms | 46 | 50 | 92.00 |
| V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 26.160s | 6.500ms | 46 | 50 | 92.00 |
| V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 6.870s | 4.585ms | 5 | 5 | 100.00 |
| V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 26.160s | 6.500ms | 46 | 50 | 92.00 |
| V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 6.870s | 4.585ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 26.160s | 6.500ms | 46 | 50 | 92.00 |
| V2S | TOTAL | 153 | 165 | 92.73 | |||
| V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 26.358s | 27 | 50 | 54.00 | |
| V3 | TOTAL | 27 | 50 | 54.00 | |||
| TOTAL | 1029 | 1110 | 92.70 |
Job returned non-zero exit code has 55 failures:
Test keymgr_sideload_protect has 2 failures.
0.keymgr_sideload_protect.95281631325395754980159368041037012927083275410390020345679341084167407774125
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sideload_protect/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:43 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
14.keymgr_sideload_protect.59388275318510877029502838201847277874969893680260105538919758153175474376888
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/14.keymgr_sideload_protect/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:45 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test keymgr_sync_async_fault_cross has 2 failures.
0.keymgr_sync_async_fault_cross.11134709008533170001783580018429020659203698116236231967914683741625440260282
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:43 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
18.keymgr_sync_async_fault_cross.62831544497073093805013779998895097668128615672722591659795250396512525291720
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:46 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test keymgr_sw_invalid_input has 3 failures.
1.keymgr_sw_invalid_input.54563875426087860750644366799888188388161272095815987474036607824913444278165
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_sw_invalid_input/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:44 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
7.keymgr_sw_invalid_input.49963761907435739882903308285642499382101026480878216020418098238751769212350
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/7.keymgr_sw_invalid_input/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:44 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 1 more failures.
Test keymgr_random has 2 failures.
2.keymgr_random.99862875762599510002357066529326524113218568544940066104731348400414818178332
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_random/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:44 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
8.keymgr_random.112058729601560696233393150758237529447106778954720859493978859931795971540110
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/8.keymgr_random/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:45 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test keymgr_lc_disable has 1 failures.
2.keymgr_lc_disable.86906358454660455208143723634056997568206302849686630528629011001520295623174
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_lc_disable/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:44 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 17 more tests.
UVM_ERROR (cip_base_vseq.sv:945) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
2.keymgr_stress_all_with_rand_reset.45635070916459271405524481469760984023410373769305043163210444909054508421259
Line 181, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1191056381 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1191056381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.keymgr_stress_all_with_rand_reset.78563030881230369754251891935874307609989825822513133386493480434200916754272
Line 154, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2343704331 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2343704331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 5 failures:
Test keymgr_sideload_kmac has 1 failures.
17.keymgr_sideload_kmac.113997088332385924284434268834460449328820767595284836558778136810171608214126
Line 157, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/17.keymgr_sideload_kmac/latest/run.log
UVM_ERROR @ 15266915 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 15266915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_sideload_otbn has 2 failures.
20.keymgr_sideload_otbn.55732663705292026562827084883374059437778185623971467360508823284568781270727
Line 86, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest/run.log
UVM_ERROR @ 14511453 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 14511453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.keymgr_sideload_otbn.66017393959744928164905368451991985936741270289711472138836723129185951662353
Line 86, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest/run.log
UVM_ERROR @ 11963436 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 11963436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_lc_disable has 1 failures.
33.keymgr_lc_disable.105165972012804463682060824276385344533471572934914034153326696590118582540358
Line 217, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/33.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 72408170 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
UVM_INFO @ 72408170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_sideload_aes has 1 failures.
36.keymgr_sideload_aes.85699795449389345657623230627001132212979043757166098547164550731269805073527
Line 82, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/36.keymgr_sideload_aes/latest/run.log
UVM_ERROR @ 6688473 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 6688473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes has 1 failures:
14.keymgr_direct_to_disabled.96498551104870006190638804115766729510842005418423932928433348334331599094730
Log /nightly/current_run/scratch/master/keymgr-sim-vcs/14.keymgr_direct_to_disabled/latest/run.log
Job timed out after 60 minutes
UVM_ERROR (cip_base_vseq.sv:849) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
22.keymgr_stress_all_with_rand_reset.61023445847446445256915598310219944339775792194551631991423302333168803205476
Line 380, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/22.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 853075809 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 853075809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout keymgr_reg_block.working_state (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
25.keymgr_lc_disable.77265522500162501830082980043831910007385820010958220426053273335874919968240
Line 274, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/25.keymgr_lc_disable/latest/run.log
UVM_FATAL @ 10154827233 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout keymgr_reg_block.working_state (addr=0x2b54dfe8, Comparison=CompareOpEq, exp_data=0x5, call_count=5)
UVM_INFO @ 10154827233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed most likely because its dependent job failed. has 1 failures: