e60097d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.063m | 19.973ms | 43 | 50 | 86.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 15.625s | 4 | 5 | 80.00 | |
| V1 | csr_rw | kmac_csr_rw | 0.940s | 85.509us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 11.770s | 1.058ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 20.417s | 3 | 5 | 60.00 | |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 17.999s | 17 | 20 | 85.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 0.940s | 85.509us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 20.417s | 3 | 5 | 60.00 | |||
| V1 | mem_walk | kmac_mem_walk | 26.637s | 4 | 5 | 80.00 | |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.180s | 37.275us | 5 | 5 | 100.00 |
| V1 | TOTAL | 101 | 115 | 87.83 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 46.155m | 431.443ms | 41 | 50 | 82.00 |
| V2 | burst_write | kmac_burst_write | 16.253m | 58.772ms | 41 | 50 | 82.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 31.260s | 2.904ms | 4 | 5 | 80.00 |
| kmac_test_vectors_sha3_256 | 19.742m | 79.889ms | 4 | 5 | 80.00 | ||
| kmac_test_vectors_sha3_384 | 23.394m | 663.499ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 15.717m | 61.177ms | 4 | 5 | 80.00 | ||
| kmac_test_vectors_shake_128 | 30.105m | 184.474ms | 4 | 5 | 80.00 | ||
| kmac_test_vectors_shake_256 | 25.407m | 59.159ms | 4 | 5 | 80.00 | ||
| kmac_test_vectors_kmac | 2.040s | 274.109us | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 13.959s | 4 | 5 | 80.00 | |||
| V2 | sideload | kmac_sideload | 5.555m | 220.806ms | 33 | 50 | 66.00 |
| V2 | app | kmac_app | 4.279m | 63.021ms | 41 | 50 | 82.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 4.018m | 29.262ms | 9 | 10 | 90.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 4.863m | 20.481ms | 37 | 50 | 74.00 |
| V2 | error | kmac_error | 6.114m | 97.216ms | 45 | 50 | 90.00 |
| V2 | key_error | kmac_key_error | 39.201s | 39 | 50 | 78.00 | |
| V2 | sideload_invalid | kmac_sideload_invalid | 24.722s | 43 | 50 | 86.00 | |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 29.240s | 10.296ms | 16 | 20 | 80.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 31.330s | 7.882ms | 16 | 20 | 80.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 37.520s | 9.398ms | 8 | 10 | 80.00 |
| V2 | lc_escalation | kmac_lc_escalation | 31.089s | 45 | 50 | 90.00 | |
| V2 | stress_all | kmac_stress_all | 34.006m | 110.193ms | 43 | 50 | 86.00 |
| V2 | intr_test | kmac_intr_test | 22.056s | 47 | 50 | 94.00 | |
| V2 | alert_test | kmac_alert_test | 28.239s | 38 | 50 | 76.00 | |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 21.255s | 19 | 20 | 95.00 | |
| V2 | tl_d_illegal_access | kmac_tl_errors | 21.255s | 19 | 20 | 95.00 | |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 15.625s | 4 | 5 | 80.00 | |
| kmac_csr_rw | 0.940s | 85.509us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 20.417s | 3 | 5 | 60.00 | |||
| kmac_same_csr_outstanding | 22.142s | 19 | 20 | 95.00 | |||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 15.625s | 4 | 5 | 80.00 | |
| kmac_csr_rw | 0.940s | 85.509us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 20.417s | 3 | 5 | 60.00 | |||
| kmac_same_csr_outstanding | 22.142s | 19 | 20 | 95.00 | |||
| V2 | TOTAL | 614 | 740 | 82.97 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.780s | 251.281us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.780s | 251.281us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.780s | 251.281us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.780s | 251.281us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.930s | 961.615us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.104m | 10.945ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 23.245s | 19 | 20 | 95.00 | |||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 23.245s | 19 | 20 | 95.00 | |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 31.089s | 45 | 50 | 90.00 | |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.063m | 19.973ms | 43 | 50 | 86.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 5.555m | 220.806ms | 33 | 50 | 66.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.780s | 251.281us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.104m | 10.945ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.104m | 10.945ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.104m | 10.945ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.063m | 19.973ms | 43 | 50 | 86.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 31.089s | 45 | 50 | 90.00 | |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.104m | 10.945ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.136m | 78.928ms | 8 | 10 | 80.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.063m | 19.973ms | 43 | 50 | 86.00 |
| V2S | TOTAL | 72 | 75 | 96.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 1.420m | 7.947ms | 5 | 10 | 50.00 |
| V3 | TOTAL | 5 | 10 | 50.00 | |||
| TOTAL | 792 | 940 | 84.26 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.25 | 99.27 | 94.49 | 99.89 | 80.28 | 97.15 | 97.83 | 97.86 |
Job returned non-zero exit code has 119 failures:
Test kmac_test_vectors_shake_256 has 1 failures.
0.kmac_test_vectors_shake_256.26962330778390070887825024131057792804563753822343682612660811086971875884905
Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 00:15 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_same_csr_outstanding has 1 failures.
0.kmac_same_csr_outstanding.95810733283544974516024197299397720456191381404606833999742273011331850511260
Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_same_csr_outstanding/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 21:05 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_sideload has 16 failures.
1.kmac_sideload.39062417004742838254149193150161581525060933281476692809965390999199537097296
Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_sideload/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 00:16 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
3.kmac_sideload.48785506355617712363777158373848223830160545786470243620006325205650747328786
Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_sideload/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 00:18 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 14 more failures.
Test kmac_test_vectors_sha3_256 has 1 failures.
1.kmac_test_vectors_sha3_256.31262737088401889727694834559569253992717705967338020321122467317663760954828
Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 00:16 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_test_vectors_kmac_xof has 1 failures.
1.kmac_test_vectors_kmac_xof.69153444644433017404631770563767872128084761131438845005854537040716116071718
Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 00:16 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 25 more tests.
Job timed out after * minutes has 25 failures:
Test kmac_stress_all has 2 failures.
1.kmac_stress_all.14406458216336722425468222235755921804633741307315608682501988959871305159428
Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all/latest/run.log
Job timed out after 180 minutes
3.kmac_stress_all.109830628586413665216951321224078166806296547434599659412754537210120136748468
Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_stress_all/latest/run.log
Job timed out after 180 minutes
Test kmac_test_vectors_sha3_224 has 1 failures.
3.kmac_test_vectors_sha3_224.28082412123287924935710517458182811965007845880910583678037250527969113012280
Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest/run.log
Job timed out after 90 minutes
Test kmac_test_vectors_shake_128 has 1 failures.
4.kmac_test_vectors_shake_128.47247385285517254111852014296987905865280038305421614248181145998329308421949
Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest/run.log
Job timed out after 90 minutes
Test kmac_entropy_refresh has 2 failures.
6.kmac_entropy_refresh.19454119025522563537648714747712044439841626163919210249101007334827174479489
Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest/run.log
Job timed out after 60 minutes
10.kmac_entropy_refresh.80814780269020304917189418297659415575756074082042900837049405500441182389531
Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest/run.log
Job timed out after 60 minutes
Test kmac_long_msg_and_output has 4 failures.
7.kmac_long_msg_and_output.37797376700639669397303425174206183707214846351893275105900279414544212539773
Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_long_msg_and_output/latest/run.log
Job timed out after 120 minutes
22.kmac_long_msg_and_output.34941091344556993263034475705182829411253896197048824338842195373240977542091
Log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/22.kmac_long_msg_and_output/latest/run.log
Job timed out after 120 minutes
... and 2 more failures.
... and 9 more tests.
UVM_ERROR (cip_base_vseq.sv:525) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 4 failures:
0.kmac_stress_all_with_rand_reset.60498534437699972675145224997931691260027446540688292367876172474422086709252
Line 328, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14122106005 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 14122106005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.kmac_stress_all_with_rand_reset.35736253151238840056892387290905988314202743674599686834636552178982161372613
Line 210, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3631724405 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 3631724405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.