e60097d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 52.740s | 8.746ms | 48 | 50 | 96.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 0.890s | 35.413us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 0.900s | 119.701us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 12.620s | 1.490ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 5.070s | 571.226us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 24.383s | 17 | 20 | 85.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 0.900s | 119.701us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 5.070s | 571.226us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.680s | 14.963us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.150s | 70.823us | 5 | 5 | 100.00 |
| V1 | TOTAL | 110 | 115 | 95.65 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 41.913m | 130.791ms | 44 | 50 | 88.00 |
| V2 | burst_write | kmac_burst_write | 10.542m | 30.172ms | 44 | 50 | 88.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 27.229m | 97.409ms | 5 | 5 | 100.00 |
| kmac_test_vectors_sha3_256 | 22.646m | 238.892ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 17.816m | 45.849ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 9.165m | 19.050ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_128 | 26.875m | 299.601ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_256 | 4.162m | 16.710ms | 4 | 5 | 80.00 | ||
| kmac_test_vectors_kmac | 22.354s | 3 | 5 | 60.00 | |||
| kmac_test_vectors_kmac_xof | 2.090s | 122.236us | 5 | 5 | 100.00 | ||
| V2 | sideload | kmac_sideload | 4.950m | 86.093ms | 43 | 50 | 86.00 |
| V2 | app | kmac_app | 3.664m | 59.112ms | 45 | 50 | 90.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 3.851m | 16.476ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 3.714m | 16.910ms | 40 | 50 | 80.00 |
| V2 | error | kmac_error | 4.906m | 169.709ms | 47 | 50 | 94.00 |
| V2 | key_error | kmac_key_error | 26.417s | 42 | 50 | 84.00 | |
| V2 | sideload_invalid | kmac_sideload_invalid | 1.450m | 10.030ms | 40 | 50 | 80.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 29.390s | 3.149ms | 19 | 20 | 95.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 28.460s | 5.078ms | 13 | 20 | 65.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 48.320s | 5.492ms | 9 | 10 | 90.00 |
| V2 | lc_escalation | kmac_lc_escalation | 34.734s | 42 | 50 | 84.00 | |
| V2 | stress_all | kmac_stress_all | 22.644m | 62.647ms | 37 | 50 | 74.00 |
| V2 | intr_test | kmac_intr_test | 20.236s | 48 | 50 | 96.00 | |
| V2 | alert_test | kmac_alert_test | 32.979s | 41 | 50 | 82.00 | |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 2.700s | 559.180us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 2.700s | 559.180us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 0.890s | 35.413us | 5 | 5 | 100.00 |
| kmac_csr_rw | 0.900s | 119.701us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 5.070s | 571.226us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 17.566s | 19 | 20 | 95.00 | |||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 0.890s | 35.413us | 5 | 5 | 100.00 |
| kmac_csr_rw | 0.900s | 119.701us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 5.070s | 571.226us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 17.566s | 19 | 20 | 95.00 | |||
| V2 | TOTAL | 640 | 740 | 86.49 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.600s | 163.091us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.600s | 163.091us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.600s | 163.091us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.600s | 163.091us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 13.852s | 19 | 20 | 95.00 | |
| V2S | tl_intg_err | kmac_sec_cm | 1.064m | 75.250ms | 3 | 5 | 60.00 |
| kmac_tl_intg_err | 3.570s | 1.003ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 3.570s | 1.003ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 34.734s | 42 | 50 | 84.00 | |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 52.740s | 8.746ms | 48 | 50 | 96.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 4.950m | 86.093ms | 43 | 50 | 86.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.600s | 163.091us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.064m | 75.250ms | 3 | 5 | 60.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.064m | 75.250ms | 3 | 5 | 60.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.064m | 75.250ms | 3 | 5 | 60.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 52.740s | 8.746ms | 48 | 50 | 96.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 34.734s | 42 | 50 | 84.00 | |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.064m | 75.250ms | 3 | 5 | 60.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 4.297m | 57.588ms | 8 | 10 | 80.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 52.740s | 8.746ms | 48 | 50 | 96.00 |
| V2S | TOTAL | 70 | 75 | 93.33 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 1.899m | 1.988ms | 5 | 10 | 50.00 |
| V3 | TOTAL | 5 | 10 | 50.00 | |||
| TOTAL | 825 | 940 | 87.77 |
Job returned non-zero exit code has 97 failures:
Test kmac_sideload has 7 failures.
0.kmac_sideload.36518868067920376275501576323235364814998862333473772440864882464028620536680
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 03:29 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
14.kmac_sideload.104431106070658360489334576207703476889558582637750156296503885119452646331655
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/14.kmac_sideload/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 03:39 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 5 more failures.
Test kmac_test_vectors_kmac has 2 failures.
0.kmac_test_vectors_kmac.72264400137155752769904046279069266445536917028687774008718915921508421017129
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 03:29 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
4.kmac_test_vectors_kmac.50103578639321183930180826369757395384631125941890541335747395818919545411759
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/4.kmac_test_vectors_kmac/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 03:31 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test kmac_entropy_mode_error has 6 failures.
0.kmac_entropy_mode_error.6653744124566225697209016932662432538404124546170200872966724563302204300514
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_entropy_mode_error/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 03:29 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
7.kmac_entropy_mode_error.34887265591329278376485277737148509036233376118049188094833885044640708246911
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/7.kmac_entropy_mode_error/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 03:34 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 4 more failures.
Test kmac_app has 4 failures.
1.kmac_app.78354431972877057022155969326435123891233953880339577164074817141759677007115
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_app/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 03:29 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
4.kmac_app.59048727439897849407416275555252992255537995594077545319897744852314954704151
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/4.kmac_app/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 03:31 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 2 more failures.
Test kmac_mubi has 1 failures.
1.kmac_mubi.14892432661945704183331897730597796872349829791756467365239557140461349819204
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_mubi/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 03:29 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 19 more tests.
Job timed out after * minutes has 10 failures:
Test kmac_test_vectors_shake_256 has 1 failures.
0.kmac_test_vectors_shake_256.58914478027600727866419177355993522225395373731660437612074974814174668463302
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest/run.log
Job timed out after 90 minutes
Test kmac_entropy_mode_error has 1 failures.
5.kmac_entropy_mode_error.39122753047922213161927210631172042365176541761115976685466295672165427643524
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/5.kmac_entropy_mode_error/latest/run.log
Job timed out after 60 minutes
Test kmac_mubi has 1 failures.
8.kmac_mubi.7143486032479385431759511295087589121610118173984732917112162447539261111584
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/8.kmac_mubi/latest/run.log
Job timed out after 60 minutes
Test kmac_long_msg_and_output has 1 failures.
14.kmac_long_msg_and_output.103225974661787914975560762765312001467984720298715629748566496427536870413566
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/14.kmac_long_msg_and_output/latest/run.log
Job timed out after 120 minutes
Test kmac_key_error has 1 failures.
18.kmac_key_error.102402542196343990460312510642902778896783193452079473835409938525303117827139
Log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/18.kmac_key_error/latest/run.log
Job timed out after 60 minutes
... and 4 more tests.
UVM_ERROR (cip_base_vseq.sv:945) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
1.kmac_stress_all_with_rand_reset.109044536830354120112695966278884922949529926483171945562659185641743392703091
Line 332, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6305449111 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6305449111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.kmac_stress_all_with_rand_reset.89858590211446181585797649831526129803856836248425480098641776328418406334882
Line 183, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3086607696 ps: (cip_base_vseq.sv:945) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3086607696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 2 failures:
4.kmac_sideload_invalid.67650965431179983287073698907337431833873504010829966328031605782496506207097
Line 78, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/4.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10044632035 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x83c56000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10044632035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.kmac_sideload_invalid.85528114080622776393448815586758684541521050547458572048401160930320356118637
Line 77, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/29.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10029837323 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8bdc8000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10029837323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 2 failures:
45.kmac_sideload_invalid.84005017163377842415205233612703039728530091139170737382206908928696604353542
Line 90, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/45.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10095770334 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5d057000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10095770334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.kmac_sideload_invalid.105289769970988812330932064721943597047821042793813633457751120440972191631638
Line 80, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/46.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10200353773 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3a890000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10200353773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:525) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
2.kmac_stress_all_with_rand_reset.37553839688603214092823823319802423909591717248246444092310438530472749275930
Line 464, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11071037584 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 11071037584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
17.kmac_sideload_invalid.97997665043605698303414617267655594332935370391916539598627678224651846070193
Line 84, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/17.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10159459679 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x44641000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10159459679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed most likely because its dependent job failed. has 1 failures: