PRIM_ESC Simulation Results

Friday September 19 2025 17:02:16 UTC

GitHub Revision: e60097d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	prim_esc_request_test	prim_esc_test	22.379s		19	20	95.00
V1	prim_ping_req_interrupted_by_esc_req_test	prim_esc_test	22.379s		19	20	95.00
V1	prim_esc_tx_integrity_errors_test	prim_esc_test	22.379s		19	20	95.00
V1	prim_esc_reverse_ping_timeout_test	prim_esc_test	22.379s		19	20	95.00
V1	prim_esc_receiver_counter_fail_test	prim_esc_test	22.379s		19	20	95.00
V1	prim_esc_handshake_with_rand_reset_test	prim_esc_test	22.379s		19	20	95.00
V1		TOTAL			19	20	95.00
		TOTAL			19	20	95.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.29	95.41	87.80	100.00	96.43	88.89	85.19

Failure Buckets

• Job returned non-zero exit code has 1 failures:
  • Test prim_esc_test has 1 failures.

    • 4.prim_esc_test.76644642610440466021959421892537702178680609792995178398173212843017816484081
      Log /nightly/current_run/scratch/master/prim_esc-sim-vcs/4.prim_esc_test/latest/run.log

        Chronologic VCS simulator copyright 1991-2023
        Contains Synopsys proprietary information.
        Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Sep 19 17:59 2025
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255