PRIM_PRESENT Simulation Results

Friday September 19 2025 17:02:16 UTC

GitHub Revision: e60097d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
	Unmapped tests	prim_present_test			0	50	0.00
		TOTAL			0	50	0.00

Failure Buckets

• Job killed most likely because its dependent job failed. has 52 failures:

  • Test prim_present_test has 50 failures.

    • 0.prim_present_test.92027400589688559025401977348625783224741866724261701351848119848038887045012
      Log /nightly/current_run/scratch/master/prim_present-sim-vcs/0.prim_present_test/latest/run.log

    • 1.prim_present_test.81597854937403678070385938620685510614808742568944147353449326409063207903110
      Log /nightly/current_run/scratch/master/prim_present-sim-vcs/1.prim_present_test/latest/run.log

    • ... and 48 more failures.

  • Test prim_present has 2 failures.

    • cov_merge
      Log /nightly/current_run/scratch/master/prim_present-sim-vcs/cov_merge/merged.vdb/cov_merge.log

    • cov_report
      Log /nightly/current_run/scratch/master/prim_present-sim-vcs/cov_report/cov_report.log

• Job returned non-zero exit code has 1 failures:

  • Test default has 1 failures.

    • default
      Log /nightly/current_run/scratch/master/prim_present-sim-vcs/default/build.log

        recompiling module prim_present_tb
        All of 28 modules done
        Feature removed during lmreread, or wrong
        SERVER line hostid.
        Check your license file.
      
        Please contact VCS Customer Support at 1-800-VERILOG for more information.
      
        CPU time: 6.951 seconds to compile
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1