e60097d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 0 | 2 | 0.00 | ||
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | rom_ctrl_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 67 | 0.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 0 | 2 | 0.00 | ||
| V2 | stress_all | rom_ctrl_stress_all | 0 | 20 | 0.00 | ||
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 0 | 2 | 0.00 | ||
| V2 | alert_test | rom_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| rom_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| rom_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 114 | 0.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 0 | 20 | 0.00 | ||
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | tl_intg_err | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| rom_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | prim_count_check | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 20 | 0.00 | ||
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 20 | 0.00 | ||
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 0 | 20 | 0.00 | ||
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 20 | 0.00 | ||
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 20 | 0.00 | ||
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 0 | 2 | 0.00 | ||
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 0 | 2 | 0.00 | ||
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 0 | 2 | 0.00 | ||
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 0 | 20 | 0.00 | ||
| rom_ctrl_kmac_err_chk | 0 | 2 | 0.00 | ||||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 0 | 20 | 0.00 | ||
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 20 | 0.00 | ||
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 0 | 20 | 0.00 | ||
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 0 | 65 | 0.00 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 0 | 20 | 0.00 | ||
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| TOTAL | 0 | 266 | 0.00 |
Job killed most likely because its dependent job failed. has 268 failures:
Test rom_ctrl_smoke has 2 failures.
0.rom_ctrl_smoke.15751577187838566101914670111384076433564968775132605533608266448445468015942
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_smoke/latest/run.log
1.rom_ctrl_smoke.86578929650583054066739370908346399154303074551250625709352714107845994295940
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_smoke/latest/run.log
Test rom_ctrl_stress_all has 20 failures.
0.rom_ctrl_stress_all.110217012852016531960938036068362540246893130147224199789254786412286656373601
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all/latest/run.log
1.rom_ctrl_stress_all.98741568245560478739326664236038421016511366275485519394003420854056211790246
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all/latest/run.log
... and 18 more failures.
Test rom_ctrl_max_throughput_chk has 2 failures.
0.rom_ctrl_max_throughput_chk.91216187156215138313612104261479483557214130433402157829112014670938184367129
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_max_throughput_chk/latest/run.log
1.rom_ctrl_max_throughput_chk.95293545176772414593545071576930072260893003421420891955504479765512014014020
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_max_throughput_chk/latest/run.log
Test rom_ctrl_corrupt_sig_fatal_chk has 20 failures.
0.rom_ctrl_corrupt_sig_fatal_chk.3828386836451215307624813594098271630964080845821292275094669225773223612968
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
1.rom_ctrl_corrupt_sig_fatal_chk.63408062944408092351082651556570551018069617322296755144868183342543731497138
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
... and 18 more failures.
Test rom_ctrl_kmac_err_chk has 2 failures.
0.rom_ctrl_kmac_err_chk.32446298213852211503805140656851832780290902224928456076909528935346638150609
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_kmac_err_chk/latest/run.log
1.rom_ctrl_kmac_err_chk.67529790038222034820535092756494183911719171180962083932878269895447300524050
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_kmac_err_chk/latest/run.log
... and 15 more tests.
Job timed out after * minutes has 1 failures:
default
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/default/build.log
Job timed out after 60 minutes
Job returned non-zero exit code has 1 failures:
cover_reg_top
Log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/cover_reg_top/build.log
recompiling module rom_ctrl_fsm_if
All of 114 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
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CPU time: 17.721 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1