e60097d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 26.443s | 1 | 2 | 50.00 | |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 34.737s | 4 | 5 | 80.00 | |
| V1 | csr_rw | rom_ctrl_csr_rw | 30.960s | 15 | 20 | 75.00 | |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 8.510s | 727.279us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 34.884s | 4 | 5 | 80.00 | |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 24.313s | 18 | 20 | 90.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 30.960s | 15 | 20 | 75.00 | |
| rom_ctrl_csr_aliasing | 34.884s | 4 | 5 | 80.00 | |||
| V1 | mem_walk | rom_ctrl_mem_walk | 22.700s | 4 | 5 | 80.00 | |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 7.820s | 555.579us | 5 | 5 | 100.00 |
| V1 | TOTAL | 56 | 67 | 83.58 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 9.470s | 310.165us | 2 | 2 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 43.400s | 7.953ms | 16 | 20 | 80.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 15.640s | 1.078ms | 2 | 2 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 12.200s | 49 | 50 | 98.00 | |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 14.430s | 295.533us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 14.430s | 295.533us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 34.737s | 4 | 5 | 80.00 | |
| rom_ctrl_csr_rw | 30.960s | 15 | 20 | 75.00 | |||
| rom_ctrl_csr_aliasing | 34.884s | 4 | 5 | 80.00 | |||
| rom_ctrl_same_csr_outstanding | 20.339s | 18 | 20 | 90.00 | |||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 34.737s | 4 | 5 | 80.00 | |
| rom_ctrl_csr_rw | 30.960s | 15 | 20 | 75.00 | |||
| rom_ctrl_csr_aliasing | 34.884s | 4 | 5 | 80.00 | |||
| rom_ctrl_same_csr_outstanding | 20.339s | 18 | 20 | 90.00 | |||
| V2 | TOTAL | 107 | 114 | 93.86 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 3.353m | 14.446ms | 18 | 20 | 90.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 1.002m | 12.136ms | 16 | 20 | 80.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 8.007m | 1.034ms | 0 | 5 | 0.00 |
| rom_ctrl_tl_intg_err | 2.031m | 845.409us | 19 | 20 | 95.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 8.007m | 1.034ms | 0 | 5 | 0.00 |
| V2S | prim_count_check | rom_ctrl_sec_cm | 8.007m | 1.034ms | 0 | 5 | 0.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.353m | 14.446ms | 18 | 20 | 90.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.353m | 14.446ms | 18 | 20 | 90.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 3.353m | 14.446ms | 18 | 20 | 90.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.353m | 14.446ms | 18 | 20 | 90.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.353m | 14.446ms | 18 | 20 | 90.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 8.007m | 1.034ms | 0 | 5 | 0.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 8.007m | 1.034ms | 0 | 5 | 0.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 26.443s | 1 | 2 | 50.00 | |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 26.443s | 1 | 2 | 50.00 | |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 26.443s | 1 | 2 | 50.00 | |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.031m | 845.409us | 19 | 20 | 95.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 3.353m | 14.446ms | 18 | 20 | 90.00 |
| rom_ctrl_kmac_err_chk | 15.640s | 1.078ms | 2 | 2 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 3.353m | 14.446ms | 18 | 20 | 90.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 3.353m | 14.446ms | 18 | 20 | 90.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 3.353m | 14.446ms | 18 | 20 | 90.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 1.002m | 12.136ms | 16 | 20 | 80.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 8.007m | 1.034ms | 0 | 5 | 0.00 |
| V2S | TOTAL | 53 | 65 | 81.54 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 6.097m | 10.448ms | 19 | 20 | 95.00 |
| V3 | TOTAL | 19 | 20 | 95.00 | |||
| TOTAL | 235 | 266 | 88.35 |
Job returned non-zero exit code has 25 failures:
Test rom_ctrl_smoke has 1 failures.
0.rom_ctrl_smoke.29284687579764705169690801124554811104818729124656854301717216119802978131547
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_smoke/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 03:16 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rom_ctrl_csr_rw has 5 failures.
0.rom_ctrl_csr_rw.90197743020173152122841100563558204964176755612369710650390016446915728101801
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_csr_rw/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 03:11 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
5.rom_ctrl_csr_rw.79841626757735408472957419848906149119536914276222071440520424572776115618132
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_csr_rw/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 03:13 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 3 more failures.
Test rom_ctrl_stress_all has 3 failures.
1.rom_ctrl_stress_all.31185865721261773311282472453360702512827137303490920587503831492634910137715
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 03:17 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
13.rom_ctrl_stress_all.94887748011471227763229045042397539040373120819332781284435901139401172738611
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/13.rom_ctrl_stress_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 03:23 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 1 more failures.
Test rom_ctrl_mem_walk has 1 failures.
2.rom_ctrl_mem_walk.98416831765407494999802384899967788994297034746944704940051672623352317339156
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_mem_walk/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 03:12 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rom_ctrl_csr_hw_reset has 1 failures.
2.rom_ctrl_csr_hw_reset.92103090333700041440890963296679197607722328240998326602955338240610012631937
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_csr_hw_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 03:12 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 9 more tests.
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 3 failures:
1.rom_ctrl_sec_cm.75326799947236171973955202462951758138760392506332721571370646480458937735590
Line 105, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 1526305ps failed at 1526305ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 1526305ps failed at 1526305ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
2.rom_ctrl_sec_cm.18918441533317811299580913537011022237748319474033075388620431110706323393613
Line 118, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 5724159ps failed at 5724159ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 5724159ps failed at 5724159ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
... and 1 more failures.
Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 2 failures:
0.rom_ctrl_sec_cm.36778051106530607276333956504154138185868321016105307049822192064848332504604
Line 429, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 448359922ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 448359922ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 448359922ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
3.rom_ctrl_sec_cm.101122983440628119711608204735374794233517449640456360763404236335046518955697
Line 106, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 2912032ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 2912032ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 2912032ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
Job timed out after * minutes has 2 failures:
Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
3.rom_ctrl_passthru_mem_tl_intg_err.7683162256782028174778119681495651233050874691621233118393062467657372261788
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
Job timed out after 60 minutes
Test rom_ctrl_stress_all has 1 failures.
6.rom_ctrl_stress_all.72037294163581246860060049981669245805299761836062599697628442920962697114109
Log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/6.rom_ctrl_stress_all/latest/run.log
Job timed out after 180 minutes