e60097d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0 | 20 | 0.00 | ||
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.590s | 16.299us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.580s | 19.521us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 1.920s | 464.180us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.710s | 59.432us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.040s | 27.786us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.580s | 19.521us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.710s | 59.432us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 55 | 75 | 73.33 | |||
| V2 | random_reset | rv_timer_random_reset | 0 | 20 | 0.00 | ||
| V2 | disabled | rv_timer_disabled | 0 | 20 | 0.00 | ||
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 0 | 10 | 0.00 | ||
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 0 | 10 | 0.00 | ||
| V2 | stress | rv_timer_stress_all | 0 | 20 | 0.00 | ||
| V2 | alert_test | rv_timer_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | rv_timer_intr_test | 17.907s | 49 | 50 | 98.00 | |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 28.545s | 19 | 20 | 95.00 | |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 28.545s | 19 | 20 | 95.00 | |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.590s | 16.299us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.580s | 19.521us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.710s | 59.432us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.740s | 47.776us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.590s | 16.299us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.580s | 19.521us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.710s | 59.432us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.740s | 47.776us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 88 | 210 | 41.90 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0 | 5 | 0.00 | ||
| rv_timer_tl_intg_err | 1.120s | 132.723us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.120s | 132.723us | 20 | 20 | 100.00 |
| V2S | TOTAL | 20 | 25 | 80.00 | |||
| V3 | min_value | rv_timer_min | 0 | 10 | 0.00 | ||
| V3 | max_value | rv_timer_max | 0 | 10 | 0.00 | ||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 0 | 20 | 0.00 | ||
| V3 | TOTAL | 0 | 40 | 0.00 | |||
| TOTAL | 163 | 350 | 46.57 |
Job killed most likely because its dependent job failed. has 186 failures:
0.rv_timer_random.47892765809230452528722571418424416201196154228745991688284453499370083290790
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random/latest/run.log
1.rv_timer_random.84893617851358316143621925366468310652889801414799421592638670328174102129523
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random/latest/run.log
... and 18 more failures.
0.rv_timer_min.59007706785170314293048306640940873373259153573693287327298380094991725573173
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
1.rv_timer_min.52492239637053703863953213369407601231073526880194371409600876228287443377935
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
... and 8 more failures.
0.rv_timer_max.82674501032815526082123546743064102279352741114008447105192209147483525254083
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
1.rv_timer_max.60538561393453915009003597164574028163367945229225855230611069731653680082649
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
... and 8 more failures.
0.rv_timer_disabled.62948207053302073069882690570494402380694498325841308878905107608439352684479
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_disabled/latest/run.log
1.rv_timer_disabled.13977751171221133666500716334317323009592345251405588000143715413738022654839
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_disabled/latest/run.log
... and 18 more failures.
0.rv_timer_cfg_update_on_fly.61285630684480481348072340532005750404965556230234595868299644708997905180528
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest/run.log
1.rv_timer_cfg_update_on_fly.102641145649438318761892066100948106366353804253133035585097316853304626695374
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest/run.log
... and 8 more failures.
Job returned non-zero exit code has 3 failures:
Test rv_timer_tl_errors has 1 failures.
15.rv_timer_tl_errors.59218655986253610858460772539876257017074173355267701440846085321878575857459
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/15.rv_timer_tl_errors/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 07:00 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rv_timer_intr_test has 1 failures.
48.rv_timer_intr_test.26798264330515677576030462981586639112517694375535345746066173838261975264186
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/48.rv_timer_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 07:00 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test rv_timer has 1 failures.
cov_merge
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/cov_merge/merged.vdb/cov_merge.log
LCA features enabled by '-lca' argument on the command line. For more
information regarding list of LCA features please refer to Chapter "LCA
features" in the VCS Release Notes
Warning-[SPECIAL_LICENSE_NEEDED] Needs special license
-merge_across_libs needs special license feature VCSTools_Net
Please check if your license server has feature VCSTools_Net available
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:231: cov_merge] Error 1
Job timed out after * minutes has 1 failures:
default
Log /nightly/current_run/scratch/master/rv_timer-sim-vcs/default/build.log
Job timed out after 60 minutes