e60097d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 6.293m | 82.131ms | 46 | 50 | 92.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.080s | 52.188us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 1.970s | 228.043us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 16.560s | 5.636ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 17.930s | 4 | 5 | 80.00 | |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 20.002s | 18 | 20 | 90.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 1.970s | 228.043us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 17.930s | 4 | 5 | 80.00 | |||
| V1 | mem_walk | spi_device_mem_walk | 22.312s | 4 | 5 | 80.00 | |
| V1 | mem_partial_access | spi_device_mem_partial_access | 1.350s | 201.610us | 5 | 5 | 100.00 |
| V1 | TOTAL | 107 | 115 | 93.04 | |||
| V2 | csb_read | spi_device_csb_read | 26.377s | 48 | 50 | 96.00 | |
| V2 | mem_parity | spi_device_mem_parity | 22.377s | 0 | 20 | 0.00 | |
| V2 | mem_cfg | spi_device_ram_cfg | 0.640s | 3.515us | 0 | 1 | 0.00 |
| V2 | tpm_read | spi_device_tpm_rw | 29.005s | 47 | 50 | 94.00 | |
| V2 | tpm_write | spi_device_tpm_rw | 29.005s | 47 | 50 | 94.00 | |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 32.674s | 44 | 50 | 88.00 | |
| spi_device_tpm_sts_read | 28.727s | 45 | 50 | 90.00 | |||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 29.220s | 39.823ms | 44 | 50 | 88.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 24.308s | 43 | 50 | 86.00 | |
| spi_device_flash_all | 4.180m | 63.082ms | 47 | 50 | 94.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 28.904s | 44 | 50 | 88.00 | |
| spi_device_flash_all | 4.180m | 63.082ms | 47 | 50 | 94.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 28.904s | 44 | 50 | 88.00 | |
| spi_device_flash_all | 4.180m | 63.082ms | 47 | 50 | 94.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 4.180m | 63.082ms | 47 | 50 | 94.00 |
| V2 | cmd_read_status | spi_device_intercept | 26.443s | 45 | 50 | 90.00 | |
| spi_device_flash_all | 4.180m | 63.082ms | 47 | 50 | 94.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 26.443s | 45 | 50 | 90.00 | |
| spi_device_flash_all | 4.180m | 63.082ms | 47 | 50 | 94.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 26.443s | 45 | 50 | 90.00 | |
| spi_device_flash_all | 4.180m | 63.082ms | 47 | 50 | 94.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 26.443s | 45 | 50 | 90.00 | |
| spi_device_flash_all | 4.180m | 63.082ms | 47 | 50 | 94.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 26.443s | 45 | 50 | 90.00 | |
| spi_device_flash_all | 4.180m | 63.082ms | 47 | 50 | 94.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 28.705s | 43 | 50 | 86.00 | |
| V2 | mailbox_command | spi_device_mailbox | 1.338m | 68.609ms | 47 | 50 | 94.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 1.338m | 68.609ms | 47 | 50 | 94.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 1.338m | 68.609ms | 47 | 50 | 94.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 27.450s | 19.286ms | 42 | 50 | 84.00 |
| spi_device_read_buffer_direct | 20.385s | 49 | 50 | 98.00 | |||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 1.338m | 68.609ms | 47 | 50 | 94.00 |
| spi_device_flash_all | 4.180m | 63.082ms | 47 | 50 | 94.00 | ||
| V2 | quad_spi | spi_device_flash_all | 4.180m | 63.082ms | 47 | 50 | 94.00 |
| V2 | dual_spi | spi_device_flash_all | 4.180m | 63.082ms | 47 | 50 | 94.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 19.696s | 46 | 50 | 92.00 | |
| V2 | write_enable_disable | spi_device_cfg_cmd | 19.696s | 46 | 50 | 92.00 | |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 6.293m | 82.131ms | 46 | 50 | 92.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 5.126m | 135.874ms | 48 | 50 | 96.00 |
| V2 | stress_all | spi_device_stress_all | 1.811h | 10.000s | 45 | 50 | 90.00 |
| V2 | alert_test | spi_device_alert_test | 26.598s | 47 | 50 | 94.00 | |
| V2 | intr_test | spi_device_intr_test | 22.616s | 47 | 50 | 94.00 | |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 16.216s | 19 | 20 | 95.00 | |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 16.216s | 19 | 20 | 95.00 | |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.080s | 52.188us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 1.970s | 228.043us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 17.930s | 4 | 5 | 80.00 | |||
| spi_device_same_csr_outstanding | 19.622s | 17 | 20 | 85.00 | |||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.080s | 52.188us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 1.970s | 228.043us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 17.930s | 4 | 5 | 80.00 | |||
| spi_device_same_csr_outstanding | 19.622s | 17 | 20 | 85.00 | |||
| V2 | TOTAL | 857 | 961 | 89.18 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.020s | 471.191us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 28.603s | 18 | 20 | 90.00 | |||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 28.603s | 18 | 20 | 90.00 | |
| V2S | TOTAL | 23 | 25 | 92.00 | |||
| Unmapped tests | spi_device_flash_mode_ignore_cmds | 5.154m | 80.715ms | 44 | 50 | 88.00 | |
| TOTAL | 1031 | 1151 | 89.57 |
Job returned non-zero exit code has 93 failures:
Test spi_device_tpm_all has 5 failures.
1.spi_device_tpm_all.63964101671020048190119673548292125604090058832829687365042736007072889249280
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_tpm_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 00:02 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
21.spi_device_tpm_all.19587014916163659388453069503037337788749227645138284642439123261785568380851
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/21.spi_device_tpm_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 00:07 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 3 more failures.
Test spi_device_pass_cmd_filtering has 6 failures.
2.spi_device_pass_cmd_filtering.99663713214943665541929383056109981428106388712041727561517383453064081555320
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/2.spi_device_pass_cmd_filtering/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 00:02 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
11.spi_device_pass_cmd_filtering.112371482768027476671751019348061809586366205656779661875763300726028512737466
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/11.spi_device_pass_cmd_filtering/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 00:04 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 4 more failures.
Test spi_device_flash_mode_ignore_cmds has 4 failures.
2.spi_device_flash_mode_ignore_cmds.91198057690834193196812364591957583167618335536191714936816932275644850103005
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 00:02 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
15.spi_device_flash_mode_ignore_cmds.72318909395308771374189756803548722027918730673889753377974477770029642562288
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 00:05 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 2 more failures.
Test spi_device_mem_walk has 1 failures.
2.spi_device_mem_walk.113796202101537627378051607582076864678809782474137741375237896733825455383199
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/2.spi_device_mem_walk/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 01:32 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test spi_device_same_csr_outstanding has 2 failures.
2.spi_device_same_csr_outstanding.28258584615903170113034477661946260152898653942995656763532061442732851646766
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/2.spi_device_same_csr_outstanding/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 01:32 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
19.spi_device_same_csr_outstanding.1515738126197230124411574560898990924727656828893584479245418474128680813072
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/19.spi_device_same_csr_outstanding/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 20 01:33 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 23 more tests.
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 18 failures:
0.spi_device_mem_parity.108026586834363430694479423059254418337801046938414268611686747415492446677756
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 1241139 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[61])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1241139 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1241139 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[957])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
1.spi_device_mem_parity.90998771036498341162317075122697959083750203403834322353803694999858114068164
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log
UVM_ERROR @ 11485685 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[71])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 11485685 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 11485685 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[967])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
... and 16 more failures.
Job timed out after * minutes has 8 failures:
Test spi_device_same_csr_outstanding has 1 failures.
5.spi_device_same_csr_outstanding.66977993806040755619009054966547060217131237742603595741789137860748881246110
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/5.spi_device_same_csr_outstanding/latest/run.log
Job timed out after 60 minutes
Test spi_device_flash_and_tpm has 1 failures.
19.spi_device_flash_and_tpm.87242071709794197149989566306570432759917564216894618497117465468508240967717
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm/latest/run.log
Job timed out after 60 minutes
Test spi_device_flash_mode_ignore_cmds has 2 failures.
21.spi_device_flash_mode_ignore_cmds.67431553068899152818128072073283452726832749664972177223197956864529749133645
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest/run.log
Job timed out after 60 minutes
32.spi_device_flash_mode_ignore_cmds.72824479681365977240758369331890464488414585333276283503345782957608251444730
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest/run.log
Job timed out after 60 minutes
Test spi_device_pass_cmd_filtering has 1 failures.
25.spi_device_pass_cmd_filtering.53932784450418426572930519429252362893891475438972636545517225621507580872759
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/25.spi_device_pass_cmd_filtering/latest/run.log
Job timed out after 60 minutes
Test spi_device_tpm_all has 1 failures.
30.spi_device_tpm_all.68965247705385174076089400633419529093907168737003462860978897247297708700290
Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/30.spi_device_tpm_all/latest/run.log
Job timed out after 60 minutes
... and 2 more tests.
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:
0.spi_device_ram_cfg.84699055628083219184236223507341487564303002229280420810919571535085752895184
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log
UVM_ERROR @ 904691 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x147b14 [101000111101100010100] vs 0x0 [0])
UVM_ERROR @ 940691 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcc6a41 [110011000110101001000001] vs 0x0 [0])
UVM_ERROR @ 1015691 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1c733 [11100011100110011] vs 0x0 [0])
UVM_ERROR @ 1074691 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbcc420 [101111001100010000100000] vs 0x0 [0])
UVM_ERROR @ 1146691 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfe0918 [111111100000100100011000] vs 0x0 [0])
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
33.spi_device_stress_all.53641389149285391340104932334581444499774317987835990799798977867162878300616
Line 119, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/33.spi_device_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed most likely because its dependent job failed. has 1 failures: