e60097d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 1.000m | 3.224ms | 39 | 50 | 78.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.700s | 56.879us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 19.994s | 19 | 20 | 95.00 | |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 1.610s | 666.429us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.680s | 61.951us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 14.258s | 18 | 20 | 90.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 19.994s | 19 | 20 | 95.00 | |
| sram_ctrl_csr_aliasing | 0.680s | 61.951us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 3.921m | 79.542ms | 44 | 50 | 88.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 1.999m | 6.315ms | 41 | 50 | 82.00 |
| V1 | TOTAL | 176 | 205 | 85.85 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 17.831m | 109.157ms | 42 | 50 | 84.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 5.228m | 25.132ms | 46 | 50 | 92.00 |
| V2 | bijection | sram_ctrl_bijection | 30.866m | 676.407ms | 34 | 50 | 68.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 14.155m | 114.584ms | 40 | 50 | 80.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 1.022m | 20.186ms | 40 | 50 | 80.00 |
| V2 | executable | sram_ctrl_executable | 14.622m | 22.689ms | 43 | 50 | 86.00 |
| V2 | partial_access | sram_ctrl_partial_access | 59.560s | 987.345us | 44 | 50 | 88.00 |
| sram_ctrl_partial_access_b2b | 7.825m | 28.339ms | 41 | 50 | 82.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 1.004m | 4.238ms | 37 | 50 | 74.00 |
| sram_ctrl_throughput_w_partial_write | 1.035m | 3.131ms | 40 | 50 | 80.00 | ||
| sram_ctrl_throughput_w_readback | 1.027m | 3.767ms | 43 | 50 | 86.00 | ||
| V2 | regwen | sram_ctrl_regwen | 13.983m | 220.867ms | 39 | 50 | 78.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 32.872s | 43 | 50 | 86.00 | |
| V2 | stress_all | sram_ctrl_stress_all | 2.007h | 407.052ms | 43 | 50 | 86.00 |
| V2 | alert_test | sram_ctrl_alert_test | 22.432s | 40 | 50 | 80.00 | |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 24.234s | 18 | 20 | 90.00 | |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 24.234s | 18 | 20 | 90.00 | |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.700s | 56.879us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 19.994s | 19 | 20 | 95.00 | |||
| sram_ctrl_csr_aliasing | 0.680s | 61.951us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 26.562s | 18 | 20 | 90.00 | |||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.700s | 56.879us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 19.994s | 19 | 20 | 95.00 | |||
| sram_ctrl_csr_aliasing | 0.680s | 61.951us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 26.562s | 18 | 20 | 90.00 | |||
| V2 | TOTAL | 651 | 790 | 82.41 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 36.570s | 70.550ms | 19 | 20 | 95.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 11.925s | 0 | 5 | 0.00 | |
| sram_ctrl_tl_intg_err | 26.620s | 19 | 20 | 95.00 | |||
| V2S | prim_count_check | sram_ctrl_sec_cm | 11.925s | 0 | 5 | 0.00 | |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 26.620s | 19 | 20 | 95.00 | |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 13.983m | 220.867ms | 39 | 50 | 78.00 |
| V2S | sec_cm_readback_config_regwen | sram_ctrl_regwen | 13.983m | 220.867ms | 39 | 50 | 78.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 19.994s | 19 | 20 | 95.00 | |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 14.622m | 22.689ms | 43 | 50 | 86.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 14.622m | 22.689ms | 43 | 50 | 86.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 14.622m | 22.689ms | 43 | 50 | 86.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 1.022m | 20.186ms | 40 | 50 | 80.00 |
| V2S | sec_cm_prim_ram_ctrl_mubi | sram_ctrl_mubi_enc_err | 39.223s | 30 | 50 | 60.00 | |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 36.570s | 70.550ms | 19 | 20 | 95.00 |
| V2S | sec_cm_mem_readback | sram_ctrl_readback_err | 26.436s | 29 | 50 | 58.00 | |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 1.000m | 3.224ms | 39 | 50 | 78.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 1.000m | 3.224ms | 39 | 50 | 78.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 14.622m | 22.689ms | 43 | 50 | 86.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 11.925s | 0 | 5 | 0.00 | |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 1.022m | 20.186ms | 40 | 50 | 80.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 11.925s | 0 | 5 | 0.00 | |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 11.925s | 0 | 5 | 0.00 | |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 1.000m | 3.224ms | 39 | 50 | 78.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 11.925s | 0 | 5 | 0.00 | |
| V2S | TOTAL | 97 | 145 | 66.90 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 3.269m | 24.153ms | 41 | 50 | 82.00 |
| V3 | TOTAL | 41 | 50 | 82.00 | |||
| TOTAL | 965 | 1190 | 81.09 |
Job returned non-zero exit code has 176 failures:
Test sram_ctrl_bijection has 11 failures.
1.sram_ctrl_bijection.101697038194804438667072189727667530064818858570462117840292832952859166786504
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_bijection/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 19:00 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
4.sram_ctrl_bijection.92704166462913095199222628401462809716632978109811732343410170507173712371761
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_bijection/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 19:01 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 9 more failures.
Test sram_ctrl_max_throughput has 12 failures.
1.sram_ctrl_max_throughput.73181242446183870697754031185869956451425779467564621087431112487364045122158
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_max_throughput/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 19:00 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
7.sram_ctrl_max_throughput.67172768095056084578136034152442912704230147842181973796282513311580767422042
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_max_throughput/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 19:06 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 10 more failures.
Test sram_ctrl_stress_pipeline has 3 failures.
2.sram_ctrl_stress_pipeline.70070793192565219794265305059529668451945904016750747086354261206446072236776
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_pipeline/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 19:00 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
42.sram_ctrl_stress_pipeline.104696216265216861535474198103538400730618637642954596694494467290613320884949
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_pipeline/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 20:09 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 1 more failures.
Test sram_ctrl_mem_partial_access has 8 failures.
2.sram_ctrl_mem_partial_access.44038802699150732476145552284272490733391734287444036937437209021636538853964
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_partial_access/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 19:00 2025
Feature removed during lmreread, or wrong
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Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
15.sram_ctrl_mem_partial_access.13647235471026738551820311829427167145081924948071754705748586054037456171546
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_partial_access/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 19:20 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 6 more failures.
Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.
2.sram_ctrl_passthru_mem_tl_intg_err.65182246177579847049684472282128034931838890723778222885424862997145382623605
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 20:26 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 24 more tests.
Job timed out after * minutes has 27 failures:
Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
2.sram_ctrl_csr_mem_rw_with_rand_reset.17161047623492504830444468179072480312313293568597633859158608493853160513663
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
Job timed out after 60 minutes
Test sram_ctrl_ram_cfg has 2 failures.
4.sram_ctrl_ram_cfg.75936031795095080295540719584010606914625758852977582551743129565445744424827
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_ram_cfg/latest/run.log
Job timed out after 60 minutes
41.sram_ctrl_ram_cfg.2650843673241139001924020094493594326156405182495113223700045833671938093518
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/41.sram_ctrl_ram_cfg/latest/run.log
Job timed out after 60 minutes
Test sram_ctrl_alert_test has 4 failures.
8.sram_ctrl_alert_test.19427651802917863094768596307183757344341316014247174484818056738308002841105
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/8.sram_ctrl_alert_test/latest/run.log
Job timed out after 60 minutes
19.sram_ctrl_alert_test.11646881372871178442762557921058418076089470907363315499597147914613285181390
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/19.sram_ctrl_alert_test/latest/run.log
Job timed out after 60 minutes
... and 2 more failures.
Test sram_ctrl_bijection has 5 failures.
12.sram_ctrl_bijection.32879832091009618057816810869585989115505558350169675234534166354394445495775
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/12.sram_ctrl_bijection/latest/run.log
Job timed out after 60 minutes
36.sram_ctrl_bijection.4183294816589404241779572648071169236483795093631946697631839459331973887250
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/36.sram_ctrl_bijection/latest/run.log
Job timed out after 60 minutes
... and 3 more failures.
Test sram_ctrl_readback_err has 2 failures.
12.sram_ctrl_readback_err.10116608862151387446399629530882212799097763208321647915277610198938002616319
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/12.sram_ctrl_readback_err/latest/run.log
Job timed out after 60 minutes
40.sram_ctrl_readback_err.52407418706883982096184623847316743017615603697088191187984796451304530149984
Log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/40.sram_ctrl_readback_err/latest/run.log
Job timed out after 60 minutes
... and 8 more tests.
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 10 failures:
3.sram_ctrl_readback_err.101363198424094614012565764540138680497563683884274884395246598714255320934508
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_readback_err/latest/run.log
UVM_ERROR @ 693605764 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x15) != exp (0x46)
UVM_INFO @ 693605764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.sram_ctrl_readback_err.67778868909101701349587305988204626957588226229424206628434395520052818638655
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_readback_err/latest/run.log
UVM_ERROR @ 1334546947 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xa) != exp (0x25)
UVM_INFO @ 1334546947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Offending 'reqfifo_rvalid' has 7 failures:
1.sram_ctrl_mubi_enc_err.96676210600489606621075903227368138590315484023683887262480294319786502582646
Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_mubi_enc_err/latest/run.log
Offending 'reqfifo_rvalid'
UVM_ERROR @ 661737203 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 661737203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.sram_ctrl_mubi_enc_err.107425959015969660825856198056900375420064434486090564604139113983137709721719
Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_mubi_enc_err/latest/run.log
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1349273255 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1349273255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Offending '(!$isunknown(rdata_o))' has 2 failures:
0.sram_ctrl_sec_cm.66116663422312985085233732598108613120240668056800071555993205720415053317263
Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 1732834 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 1732834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.sram_ctrl_sec_cm.110555635422719724905209875804139516345770359653311296806912683266824751021828
Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 11973310 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 11973310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))' has 1 failures:
1.sram_ctrl_sec_cm.47798743914293243416611547846004134805292800809926972070390749536261188944793
Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 4164644 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 4164644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
4.sram_ctrl_sec_cm.90264415211550093571926951594311532946637887091808367561533338447833741870028
Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log
UVM_ERROR @ 8070791 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 8070791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@5098) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
15.sram_ctrl_readback_err.39520139395961217562469771754736623934741209789432094395490684502020873574195
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/15.sram_ctrl_readback_err/latest/run.log
UVM_ERROR @ 668172100 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@5098) { a_addr: 'hf58c3b48 a_data: 'h3b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h1 a_user: 'h241dc d_param: 'h0 d_source: 'h13 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 668172100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@5124) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
33.sram_ctrl_mubi_enc_err.18669220846218317081664132342001087525590256064368085668420331734753806645117
Line 110, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/33.sram_ctrl_mubi_enc_err/latest/run.log
UVM_ERROR @ 664161909 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@5124) { a_addr: 'he382c4fc a_data: 'h50 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3b a_opcode: 'h0 a_user: 'h2469a d_param: 'h0 d_source: 'h3b d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 664161909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed most likely because its dependent job failed. has 1 failures: