e60097d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 1.102m | 7.218ms | 41 | 50 | 82.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.650s | 24.926us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.640s | 52.543us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 1.710s | 688.375us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.650s | 72.803us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 1.420s | 36.394us | 17 | 20 | 85.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.640s | 52.543us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.650s | 72.803us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 30.726s | 42 | 50 | 84.00 | |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 32.453s | 38 | 50 | 76.00 | |
| V1 | TOTAL | 173 | 205 | 84.39 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 16.260m | 85.590ms | 45 | 50 | 90.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 4.211m | 15.330ms | 45 | 50 | 90.00 |
| V2 | bijection | sram_ctrl_bijection | 1.005m | 64.846ms | 46 | 50 | 92.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 13.938m | 9.283ms | 44 | 50 | 88.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 26.957s | 41 | 50 | 82.00 | |
| V2 | executable | sram_ctrl_executable | 12.172m | 206.927ms | 47 | 50 | 94.00 |
| V2 | partial_access | sram_ctrl_partial_access | 52.840s | 2.507ms | 41 | 50 | 82.00 |
| sram_ctrl_partial_access_b2b | 7.887m | 372.609ms | 44 | 50 | 88.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 54.970s | 259.400us | 44 | 50 | 88.00 |
| sram_ctrl_throughput_w_partial_write | 57.420s | 592.638us | 40 | 50 | 80.00 | ||
| sram_ctrl_throughput_w_readback | 58.000s | 624.634us | 47 | 50 | 94.00 | ||
| V2 | regwen | sram_ctrl_regwen | 14.020m | 31.620ms | 42 | 50 | 84.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 28.540s | 44 | 50 | 88.00 | |
| V2 | stress_all | sram_ctrl_stress_all | 50.439m | 94.191ms | 41 | 50 | 82.00 |
| V2 | alert_test | sram_ctrl_alert_test | 33.473s | 38 | 50 | 76.00 | |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 3.270s | 2.268ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 3.270s | 2.268ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.650s | 24.926us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.640s | 52.543us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.650s | 72.803us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.710s | 21.907us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.650s | 24.926us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.640s | 52.543us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.650s | 72.803us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.710s | 21.907us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 689 | 790 | 87.22 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 2.770s | 881.323us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 14.362s | 0 | 5 | 0.00 | |
| sram_ctrl_tl_intg_err | 15.605s | 18 | 20 | 90.00 | |||
| V2S | prim_count_check | sram_ctrl_sec_cm | 14.362s | 0 | 5 | 0.00 | |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 15.605s | 18 | 20 | 90.00 | |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 14.020m | 31.620ms | 42 | 50 | 84.00 |
| V2S | sec_cm_readback_config_regwen | sram_ctrl_regwen | 14.020m | 31.620ms | 42 | 50 | 84.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.640s | 52.543us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 12.172m | 206.927ms | 47 | 50 | 94.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 12.172m | 206.927ms | 47 | 50 | 94.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 12.172m | 206.927ms | 47 | 50 | 94.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 26.957s | 41 | 50 | 82.00 | |
| V2S | sec_cm_prim_ram_ctrl_mubi | sram_ctrl_mubi_enc_err | 28.227s | 36 | 50 | 72.00 | |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 2.770s | 881.323us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_readback | sram_ctrl_readback_err | 24.537s | 35 | 50 | 70.00 | |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 1.102m | 7.218ms | 41 | 50 | 82.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 1.102m | 7.218ms | 41 | 50 | 82.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 12.172m | 206.927ms | 47 | 50 | 94.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 14.362s | 0 | 5 | 0.00 | |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 26.957s | 41 | 50 | 82.00 | |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 14.362s | 0 | 5 | 0.00 | |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 14.362s | 0 | 5 | 0.00 | |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 1.102m | 7.218ms | 41 | 50 | 82.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 14.362s | 0 | 5 | 0.00 | |
| V2S | TOTAL | 109 | 145 | 75.17 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 7.747m | 13.324ms | 43 | 50 | 86.00 |
| V3 | TOTAL | 43 | 50 | 86.00 | |||
| TOTAL | 1014 | 1190 | 85.21 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.64 | 99.07 | 92.90 | 85.37 | 100.00 | 97.98 | 95.79 | 98.33 |
Job returned non-zero exit code has 128 failures:
Test sram_ctrl_access_during_key_req has 4 failures.
0.sram_ctrl_access_during_key_req.75293870384130315081675434380171332592360387364219282493185855715773371590186
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 21:42 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
16.sram_ctrl_access_during_key_req.113650423080095863258466955104561959267472547301537147359751156623481985091094
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/16.sram_ctrl_access_during_key_req/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 22:45 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 2 more failures.
Test sram_ctrl_stress_all has 7 failures.
0.sram_ctrl_stress_all.49944590138416997007769890182012898493564758851996070547947851475511701723444
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 21:43 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
5.sram_ctrl_stress_all.61589903130349818405844620676640770659820328527982754834933926862765422414425
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 22:07 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 5 more failures.
Test sram_ctrl_sec_cm has 1 failures.
0.sram_ctrl_sec_cm.51034408928278952559384467547519739966218559016081209432760507264148263805819
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 21:44 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test sram_ctrl_bijection has 4 failures.
1.sram_ctrl_bijection.90271691315535518699316516701751168178481454371525309695786558845908492368482
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_bijection/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 21:44 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
2.sram_ctrl_bijection.63335218115207204105808132957939265700574467781624185697092239544702375110108
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_bijection/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 21:49 2025
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 2 more failures.
Test sram_ctrl_alert_test has 11 failures.
1.sram_ctrl_alert_test.64012623228415552541067628976676242119640614067976604378555392380138126047997
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_alert_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 21:49 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
7.sram_ctrl_alert_test.102700432384317066935363012887338666240446336507068634177957719148654418581751
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_alert_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 22:13 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 9 more failures.
... and 18 more tests.
Job timed out after * minutes has 27 failures:
Test sram_ctrl_stress_pipeline has 1 failures.
0.sram_ctrl_stress_pipeline.90773158794726266968581583930430391456578139193865645582243708099659880338098
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_pipeline/latest/run.log
Job timed out after 60 minutes
Test sram_ctrl_max_throughput has 2 failures.
0.sram_ctrl_max_throughput.44649909989629042921598129898290013985116979840552628047070992296304805166444
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_max_throughput/latest/run.log
Job timed out after 60 minutes
17.sram_ctrl_max_throughput.38007281357870863694034423198585736756861504295161458777351454814813834064322
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/17.sram_ctrl_max_throughput/latest/run.log
Job timed out after 60 minutes
Test sram_ctrl_mem_partial_access has 1 failures.
0.sram_ctrl_mem_partial_access.62830524411827111870146876266526613379619758706616146055036657856947513659293
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_partial_access/latest/run.log
Job timed out after 60 minutes
Test sram_ctrl_throughput_w_partial_write has 3 failures.
1.sram_ctrl_throughput_w_partial_write.106571030397701367557537880477787964389785565477526911374594774136664677301782
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest/run.log
Job timed out after 60 minutes
34.sram_ctrl_throughput_w_partial_write.189006106463080497477246369899685062820878765992861406602052041695399865412
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
Test sram_ctrl_lc_escalation has 3 failures.
1.sram_ctrl_lc_escalation.72441478024314006985358381808301571823757670917156805215326627747940637406168
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest/run.log
Job timed out after 60 minutes
20.sram_ctrl_lc_escalation.93799412602442524415586065816524372886753413960874136678961231890153225899691
Log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/20.sram_ctrl_lc_escalation/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
... and 12 more tests.
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 7 failures:
1.sram_ctrl_readback_err.87435282168411038511750798571660205182650966602167820809795801493973417752154
Line 105, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_readback_err/latest/run.log
UVM_ERROR @ 48015189 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7d) != exp (0x58)
UVM_INFO @ 48015189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.sram_ctrl_readback_err.33491486054271683704225677396712009600400042310943939051358689050970299979018
Line 105, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_readback_err/latest/run.log
UVM_ERROR @ 50536458 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x76) != exp (0x2a)
UVM_INFO @ 50536458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Offending 'reqfifo_rvalid' has 6 failures:
16.sram_ctrl_mubi_enc_err.75229007321711658993860957847737777627817691521276057671262475566093981729326
Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/16.sram_ctrl_mubi_enc_err/latest/run.log
Offending 'reqfifo_rvalid'
UVM_ERROR @ 25877260 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 25877260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.sram_ctrl_mubi_enc_err.65785058194408993479268667847996980234034855901287066392673780237521621305370
Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/24.sram_ctrl_mubi_enc_err/latest/run.log
Offending 'reqfifo_rvalid'
UVM_ERROR @ 92214877 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 92214877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:
1.sram_ctrl_sec_cm.94649760947349026345661816086130527818024715544995541002141367640733074804601
Line 106, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
UVM_ERROR @ 5645992 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 5645992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.sram_ctrl_sec_cm.16568996923920472719296659760870304925787977402643623741105043051609077261388
Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
UVM_ERROR @ 8927081 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 8927081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '(depth_o <= *'(Depth))' has 1 failures:
3.sram_ctrl_sec_cm.90162406562750492024502744060338511897175751791407370059711322926037908791798
Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 4066529 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 4066529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
3.sram_ctrl_tl_intg_err.14586865772995376807234404698138156095518747277533280282789307320141680872085
Line 168, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_tl_intg_err/latest/run.log
UVM_ERROR @ 173097197 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 173097197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: * has 1 failures:
8.sram_ctrl_csr_mem_rw_with_rand_reset.110479758078738795008056839204543490386284878015396091251043517158644902599853
Line 105, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 23635491 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: 0x0
UVM_INFO @ 23635491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
9.sram_ctrl_csr_mem_rw_with_rand_reset.71965110221968567835916970950863739829885322086497589412671211608055210359191
Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 281091523 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (2 [0x2] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 281091523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:
11.sram_ctrl_csr_mem_rw_with_rand_reset.52257151091051570120766933647595597057216341661407161986718723165573615300735
Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 64312477 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
UVM_INFO @ 64312477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---