e60097d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | uart_smoke | 22.878s | 46 | 50 | 92.00 | |
| V1 | csr_hw_reset | uart_csr_hw_reset | 0.830s | 1.071ms | 5 | 5 | 100.00 |
| V1 | csr_rw | uart_csr_rw | 28.207s | 15 | 20 | 75.00 | |
| V1 | csr_bit_bash | uart_csr_bit_bash | 21.971s | 4 | 5 | 80.00 | |
| V1 | csr_aliasing | uart_csr_aliasing | 0.700s | 62.488us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | uart_csr_mem_rw_with_rand_reset | 20.425s | 18 | 20 | 90.00 | |
| V1 | regwen_csr_and_corresponding_lockable_csr | uart_csr_rw | 28.207s | 15 | 20 | 75.00 | |
| uart_csr_aliasing | 0.700s | 62.488us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 93 | 105 | 88.57 | |||
| V2 | base_random_seq | uart_tx_rx | 2.333m | 130.562ms | 43 | 50 | 86.00 |
| V2 | parity | uart_smoke | 22.878s | 46 | 50 | 92.00 | |
| uart_tx_rx | 2.333m | 130.562ms | 43 | 50 | 86.00 | ||
| V2 | parity_error | uart_intr | 4.987m | 187.806ms | 46 | 50 | 92.00 |
| uart_rx_parity_err | 4.200m | 156.311ms | 47 | 50 | 94.00 | ||
| V2 | watermark | uart_tx_rx | 2.333m | 130.562ms | 43 | 50 | 86.00 |
| uart_intr | 4.987m | 187.806ms | 46 | 50 | 92.00 | ||
| V2 | fifo_full | uart_fifo_full | 5.346m | 148.850ms | 45 | 50 | 90.00 |
| V2 | fifo_overflow | uart_fifo_overflow | 3.759m | 183.657ms | 46 | 50 | 92.00 |
| V2 | fifo_reset | uart_fifo_reset | 7.572m | 107.981ms | 266 | 300 | 88.67 |
| V2 | rx_frame_err | uart_intr | 4.987m | 187.806ms | 46 | 50 | 92.00 |
| V2 | rx_break_err | uart_intr | 4.987m | 187.806ms | 46 | 50 | 92.00 |
| V2 | rx_timeout | uart_intr | 4.987m | 187.806ms | 46 | 50 | 92.00 |
| V2 | perf | uart_perf | 14.513m | 27.758ms | 45 | 50 | 90.00 |
| V2 | sys_loopback | uart_loopback | 28.572s | 41 | 50 | 82.00 | |
| V2 | line_loopback | uart_loopback | 28.572s | 41 | 50 | 82.00 | |
| V2 | rx_noise_filter | uart_noise_filter | 1.414m | 506.003ms | 6 | 50 | 12.00 |
| V2 | rx_start_bit_filter | uart_rx_start_bit_filter | 42.090s | 39.350ms | 42 | 50 | 84.00 |
| V2 | tx_overide | uart_tx_ovrd | 25.040s | 7.082ms | 45 | 50 | 90.00 |
| V2 | rx_oversample | uart_rx_oversample | 42.120s | 7.434ms | 49 | 50 | 98.00 |
| V2 | long_b2b_transfer | uart_long_xfer_wo_dly | 11.613m | 139.666ms | 45 | 50 | 90.00 |
| V2 | stress_all | uart_stress_all | 21.130m | 463.545ms | 37 | 50 | 74.00 |
| V2 | alert_test | uart_alert_test | 36.769s | 39 | 50 | 78.00 | |
| V2 | intr_test | uart_intr_test | 20.491s | 47 | 50 | 94.00 | |
| V2 | tl_d_oob_addr_access | uart_tl_errors | 22.324s | 18 | 20 | 90.00 | |
| V2 | tl_d_illegal_access | uart_tl_errors | 22.324s | 18 | 20 | 90.00 | |
| V2 | tl_d_outstanding_access | uart_csr_hw_reset | 0.830s | 1.071ms | 5 | 5 | 100.00 |
| uart_csr_rw | 28.207s | 15 | 20 | 75.00 | |||
| uart_csr_aliasing | 0.700s | 62.488us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 15.936s | 18 | 20 | 90.00 | |||
| V2 | tl_d_partial_access | uart_csr_hw_reset | 0.830s | 1.071ms | 5 | 5 | 100.00 |
| uart_csr_rw | 28.207s | 15 | 20 | 75.00 | |||
| uart_csr_aliasing | 0.700s | 62.488us | 5 | 5 | 100.00 | ||
| uart_same_csr_outstanding | 15.936s | 18 | 20 | 90.00 | |||
| V2 | TOTAL | 925 | 1090 | 84.86 | |||
| V2S | tl_intg_err | uart_sec_cm | 0.780s | 214.258us | 5 | 5 | 100.00 |
| uart_tl_intg_err | 1.110s | 95.678us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | uart_tl_intg_err | 1.110s | 95.678us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | uart_stress_all_with_rand_reset | 1.493m | 5.876ms | 83 | 100 | 83.00 |
| V3 | TOTAL | 83 | 100 | 83.00 | |||
| TOTAL | 1126 | 1320 | 85.30 |
Job returned non-zero exit code has 117 failures:
Test uart_tl_errors has 2 failures.
0.uart_tl_errors.109373684450202653232523952061136691357364965377456596031351442082925014707468
Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_tl_errors/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:42 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
7.uart_tl_errors.20628629950524026161200941899047284609996944372876012165579674264052198251124
Log /nightly/current_run/scratch/master/uart-sim-vcs/7.uart_tl_errors/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:43 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
Test uart_intr_test has 3 failures.
0.uart_intr_test.58017952831168853222905184409240673766376901871595791487584280742016285712256
Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:42 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
6.uart_intr_test.20790636290868678789431371080817177834985261520733937068147160791065227596431
Log /nightly/current_run/scratch/master/uart-sim-vcs/6.uart_intr_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:43 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 1 more failures.
Test uart_csr_rw has 5 failures.
0.uart_csr_rw.54285412346293836756362925199840737786696900166254876192190013687981979179680
Log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_csr_rw/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:42 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
10.uart_csr_rw.82703930067078893789616782747446235675311885333087218682780097066054899877479
Log /nightly/current_run/scratch/master/uart-sim-vcs/10.uart_csr_rw/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:43 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 3 more failures.
Test uart_rx_start_bit_filter has 8 failures.
2.uart_rx_start_bit_filter.64326239183499758996891309552618620793560480640584949047997982732113744971165
Log /nightly/current_run/scratch/master/uart-sim-vcs/2.uart_rx_start_bit_filter/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:10 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
4.uart_rx_start_bit_filter.78684439641189324723260690558687088950148399042478257512097345543902552873122
Log /nightly/current_run/scratch/master/uart-sim-vcs/4.uart_rx_start_bit_filter/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:11 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 6 more failures.
Test uart_alert_test has 9 failures.
2.uart_alert_test.92177104837040888696751200155668475248397035033043604818862088351252424500061
Log /nightly/current_run/scratch/master/uart-sim-vcs/2.uart_alert_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:10 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
6.uart_alert_test.28345394434970588846346490943550965356518133989727823871501001649039203893790
Log /nightly/current_run/scratch/master/uart-sim-vcs/6.uart_alert_test/latest/run.log
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 19 18:12 2025
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:186: simulate] Error 255
... and 7 more failures.
... and 19 more tests.
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 32 failures:
2.uart_noise_filter.21761632143492868783698075924229563895702627785872852594963284038810319980784
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/2.uart_noise_filter/latest/run.log
UVM_ERROR @ 38960485 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 43671698 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 44042822 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 44393328 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 44743834 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
5.uart_noise_filter.114657511466654716734987066196800451414899418942980948837465725729825736459378
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/5.uart_noise_filter/latest/run.log
UVM_ERROR @ 16745457 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 23145457 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 119745457 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 119785457 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 119825457 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 241 [0xf1]) reg name: uart_reg_block.rdata
... and 18 more failures.
7.uart_stress_all_with_rand_reset.73349492552089544984881603221180366156391910266345226206450081671855481932889
Line 185, in log /nightly/current_run/scratch/master/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2842731285 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2842731285 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 2844468657 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/120
UVM_INFO @ 2930761500 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/120
UVM_INFO @ 2987710938 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 8/120
46.uart_stress_all_with_rand_reset.68034653942297136662172973488355017610128636247903424008301386722436144596684
Line 172, in log /nightly/current_run/scratch/master/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5279035717 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 5279958805 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_INFO @ 5355209708 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/726
UVM_ERROR @ 5460807129 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 5461191749 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
... and 3 more failures.
11.uart_stress_all.47310725840398641960472301910357352792875096607718537325984460671475956897362
Line 82, in log /nightly/current_run/scratch/master/uart-sim-vcs/11.uart_stress_all/latest/run.log
UVM_ERROR @ 45584259143 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 45587159143 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 45591759143 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 45592759143 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 45593359143 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
17.uart_stress_all.45126995345296913760056473851879831687175621003585603376285517248898880239742
Line 79, in log /nightly/current_run/scratch/master/uart-sim-vcs/17.uart_stress_all/latest/run.log
UVM_ERROR @ 14154119059 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 14155400350 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 14155858698 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 14156296212 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 14156733726 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
... and 5 more failures.
Job timed out after * minutes has 16 failures:
Test uart_rx_parity_err has 1 failures.
3.uart_rx_parity_err.89772339153871207169898898092633039415456553466225384464104982969882363263543
Log /nightly/current_run/scratch/master/uart-sim-vcs/3.uart_rx_parity_err/latest/run.log
Job timed out after 60 minutes
Test uart_csr_mem_rw_with_rand_reset has 1 failures.
3.uart_csr_mem_rw_with_rand_reset.21294831110497076420303537033453342724049949135772041445788037043165416809134
Log /nightly/current_run/scratch/master/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest/run.log
Job timed out after 60 minutes
Test uart_tx_rx has 1 failures.
7.uart_tx_rx.50763355025023318860202749684869894549342150934815276618880526384815625380002
Log /nightly/current_run/scratch/master/uart-sim-vcs/7.uart_tx_rx/latest/run.log
Job timed out after 60 minutes
Test uart_alert_test has 2 failures.
8.uart_alert_test.70530856378088733916239884177405308226685413345773824142049023267861264190554
Log /nightly/current_run/scratch/master/uart-sim-vcs/8.uart_alert_test/latest/run.log
Job timed out after 60 minutes
49.uart_alert_test.34936388217313078656759749060008125404457399491541079174935667205200261188939
Log /nightly/current_run/scratch/master/uart-sim-vcs/49.uart_alert_test/latest/run.log
Job timed out after 60 minutes
Test uart_perf has 1 failures.
18.uart_perf.113201662761334632477975137573429025751165957984243583281690833750115240004940
Log /nightly/current_run/scratch/master/uart-sim-vcs/18.uart_perf/latest/run.log
Job timed out after 60 minutes
... and 6 more tests.
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 10 failures:
Test uart_noise_filter has 8 failures.
0.uart_noise_filter.6467975303151913727316889299087491500408046168093054435250069702563344403279
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log
UVM_ERROR @ 313794977 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 313838455 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 313881933 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 247 [0xf7]) reg name: uart_reg_block.rdata
UVM_ERROR @ 313968889 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 314012367 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
13.uart_noise_filter.23629859314403785458927068516877265623509672207504557229211289101571008666736
Line 78, in log /nightly/current_run/scratch/master/uart-sim-vcs/13.uart_noise_filter/latest/run.log
UVM_ERROR @ 102233348042 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 102233448042 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 102233548042 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (20 [0x14] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 102614648042 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 102614648042 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
... and 6 more failures.
Test uart_stress_all has 1 failures.
13.uart_stress_all.57486442432099043807420116899831003053569876884338816516102230848466486697025
Line 76, in log /nightly/current_run/scratch/master/uart-sim-vcs/13.uart_stress_all/latest/run.log
UVM_ERROR @ 1490171536 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 19, clk_pulses: 0
UVM_ERROR @ 1490181953 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1490234038 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (254 [0xfe] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 1490244455 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1490338208 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (254 [0xfe] vs 227 [0xe3]) reg name: uart_reg_block.rdata
Test uart_stress_all_with_rand_reset has 1 failures.
79.uart_stress_all_with_rand_reset.77762952587308366630430300662486325936402591217882708785791415243332658827410
Line 130, in log /nightly/current_run/scratch/master/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2172387023 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 2172417023 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 2172427023 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 191 [0xbf]) reg name: uart_reg_block.rdata
UVM_INFO @ 2224227023 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/365
UVM_ERROR @ 2264937023 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 10 failures:
20.uart_noise_filter.73380518683132498831980160190607726446647157167788604165529288300044166994460
Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/20.uart_noise_filter/latest/run.log
UVM_ERROR @ 319246247 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 319246247 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 319246247 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 347503216 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 4
UVM_ERROR @ 347513525 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
24.uart_noise_filter.87577245369778397082494385354042482756644695634335934547915110502759891837249
Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/24.uart_noise_filter/latest/run.log
UVM_ERROR @ 11792756118 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 11792756118 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 11792756118 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 11851687229 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 11851732683 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (115 [0x73] vs 253 [0xfd]) reg name: uart_reg_block.rdata
... and 7 more failures.
24.uart_long_xfer_wo_dly.113369247237859951703389188172589964923796890785616176431672878179258478027573
Line 73, in log /nightly/current_run/scratch/master/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest/run.log
UVM_ERROR @ 41705052984 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 42312116664 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 42401940912 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 42817826592 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 44672723784 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 4 failures:
Test uart_noise_filter has 2 failures.
4.uart_noise_filter.30598393821766541174599836620979104381254457229479289964966427121252233394002
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/4.uart_noise_filter/latest/run.log
UVM_ERROR @ 300542264 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 384126266 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 384126266 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 393709676 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 393709676 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
8.uart_noise_filter.28075726255045260379065915073007884342567513640604697443777107784049227055213
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/8.uart_noise_filter/latest/run.log
UVM_ERROR @ 398942762 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 398942762 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 398942762 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
UVM_ERROR @ 582235895 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 582235895 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
Test uart_stress_all_with_rand_reset has 2 failures.
39.uart_stress_all_with_rand_reset.72884279531643730475467912416776041234444859234225875804208179859947253659567
Line 130, in log /nightly/current_run/scratch/master/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9361272692 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 9361272692 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_ERROR @ 9445952692 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 9445952692 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_ERROR @ 9445952692 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
68.uart_stress_all_with_rand_reset.80891794379487698740527873357376395522704475247416208314941901580770926375844
Line 106, in log /nightly/current_run/scratch/master/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 927823456 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 927823456 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 1014955412 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5, clk_pulses: 0
UVM_ERROR @ 1014965616 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1014975820 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 4 failures:
Test uart_perf has 1 failures.
29.uart_perf.35293802368472313450650972566383854570872970162134630390613007165108534113527
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/29.uart_perf/latest/run.log
UVM_ERROR @ 3815413 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
UVM_INFO @ 5045260693 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/7
UVM_INFO @ 6573347137 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/7
UVM_INFO @ 6660068016 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/7
UVM_INFO @ 11386721326 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/7
Test uart_stress_all_with_rand_reset has 2 failures.
67.uart_stress_all_with_rand_reset.59384919860084442954394520552137154824506507684273764761315540019069280839037
Line 93, in log /nightly/current_run/scratch/master/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2824909578 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
UVM_INFO @ 3165703971 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/334
UVM_INFO @ 3303147444 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/5
UVM_INFO @ 3378330672 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/334
UVM_INFO @ 3758542047 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/5
96.uart_stress_all_with_rand_reset.3596865344047447246491876226172973688099130932593387186790971891757079847180
Line 133, in log /nightly/current_run/scratch/master/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15313406532 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
UVM_INFO @ 16750293984 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/873
UVM_INFO @ 17724404121 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/873
UVM_INFO @ 18986069526 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/873
UVM_INFO @ 19416735762 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/9
Test uart_fifo_reset has 1 failures.
245.uart_fifo_reset.87622272910573010571843506251376204911739058652256948099050150211605046832694
Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/245.uart_fifo_reset/latest/run.log
UVM_ERROR @ 791200 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
UVM_INFO @ 173421200 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/6
UVM_INFO @ 1246541200 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/6
UVM_INFO @ 8849211200 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/6
UVM_INFO @ 8955471200 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/6
UVM_ERROR (cip_base_vseq.sv:849) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
21.uart_stress_all_with_rand_reset.91658533197122828295451235159906718290789416872201764356331659535575705470343
Line 74, in log /nightly/current_run/scratch/master/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5099397 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5099397 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 5129863 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_smoke_vseq] finished run 1/2
UVM_INFO @ 5129863 ps: (uart_stress_all_vseq.sv:53) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_stress_all_vseq] starting stress_all sub-sequence uart_perf_vseq
34.uart_stress_all_with_rand_reset.113646092694530337943261592808747313767125651775930353650071397114336608891127
Line 160, in log /nightly/current_run/scratch/master/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5267154741 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5267154741 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 9/10
UVM_INFO @ 5267219367 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_smoke_vseq] finished run 1/2
UVM_INFO @ 5267219367 ps: (uart_stress_all_vseq.sv:53) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_stress_all_vseq] starting stress_all sub-sequence uart_tx_rx_vseq
Job killed most likely because its dependent job failed. has 1 failures: