CHIP Simulation Results

Friday September 19 2025 17:02:16 UTC

GitHub Revision: e60097d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	16.866s		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	16.866s		0	5	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	16.801s		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	17.559s		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	16.582s		0	5	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.343m	6.076ms	1	3	33.33
V1	chip_sw_gpio_in	chip_sw_gpio	7.343m	6.076ms	1	3	33.33
V1	chip_sw_gpio_irq	chip_sw_gpio	7.343m	6.076ms	1	3	33.33
V1	chip_sw_example_tests	chip_sw_example_rom	44.467s		0	3	0.00
		chip_sw_example_manufacturer	19.464s		0	3	0.00
		chip_sw_example_concurrency	4.439m	5.504ms	1	3	33.33
		chip_sw_uart_smoketest_signed	59.088s		0	3	0.00
V1	csr_bit_bash	chip_csr_bit_bash	11.010s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	9.900s		0	3	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.900s		0	3	0.00
V1	xbar_smoke	xbar_smoke	42.508s		78	100	78.00
V1		TOTAL			80	156	51.28
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	16.587s		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.915m	9.108ms	1	3	33.33
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.466m	4.066ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	16.096s		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	15.617s		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	16.652s		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	16.138s		0	3	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.180s		0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.180s		0	10	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	14.364s		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	16.806s		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	15.984s		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	15.984s		0	6	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	4.424m	5.237ms	0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	4.566m	4.584ms	0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.791m	14.297ms	0	3	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	17.184s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	17.304s		0	3	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	21.084m	32.321ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.568m	5.260ms	1	3	33.33
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	32.732m	18.019ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	32.732m	18.019ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	2.848m		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.473m	4.726ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.473m	4.726ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.301m	18.019ms	0	5	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.432m	4.705ms	2	3	66.67
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.595m	4.608ms	2	3	66.67
		chip_sw_aes_idle	5.960m	5.489ms	2	3	66.67
		chip_sw_hmac_enc_idle	4.368m	4.778ms	1	3	33.33
		chip_sw_kmac_idle	4.957m	5.590ms	1	3	33.33
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	16.599m	12.027ms	0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	17.210m	12.023ms	1	3	33.33
		chip_sw_clkmgr_off_kmac_trans	19.069m	12.019ms	0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	19.214m	11.780ms	1	3	33.33
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	12.605s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	53.598s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	43.506s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	36.171s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.413s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	20.768s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.161s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.605s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	53.598s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	43.506s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	36.171s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.413s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	20.768s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.161s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	2.509m		0	3	0.00
		chip_sw_aes_enc_jitter_en	37.800s	10.260us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	46.464s		0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	53.790s	10.120us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	36.526s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	26.802s		0	3	0.00
		chip_sw_clkmgr_jitter	4.137m	3.688ms	2	3	66.67
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.863m	4.320ms	2	3	66.67
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	16.312s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	46.290s	10.360us	0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	40.710s	10.320us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	44.970s	10.400us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	50.520s	10.120us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	45.660s	10.320us	0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	17.463s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.690s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	17.588s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	18.555s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	34.348m	17.063ms	70	100	70.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.420m	10.671ms	1	3	33.33
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.473m	4.726ms	0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	2.459m		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.420m	10.671ms	1	3	33.33
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	20.626s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	16.379s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	16.009s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	20.925s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	17.649s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	34.348m	17.063ms	70	100	70.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.791m	14.297ms	0	3	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	31.238m	20.027ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	46.036s		0	3	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	7.900m	6.528ms	0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.488m	3.386ms	1	3	33.33
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	34.348m	17.063ms	70	100	70.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.497m		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	2.557m		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	34.348m	17.063ms	70	100	70.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.342m		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	7.900m	6.528ms	0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	2.577m		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.552m		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	2.735m		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	3.181m		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	3.627m		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.655m		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	2.557m		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	18.016s		0	15	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	14.871s		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	18.016s		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	18.016s		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	18.016s		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.912m	6.519ms	0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.338s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.819s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.469s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.817s		0	3	0.00
		chip_sw_lc_ctrl_transition	18.016s		0	15	0.00
		chip_sw_keymgr_dpe_key_derivation	7.838m	10.280ms	0	3	0.00
		chip_sw_rom_ctrl_integrity_check	1.939m		0	3	0.00
		chip_sw_sram_ctrl_execution_main	16.162s		0	3	0.00
		chip_prim_tl_access	14.559m	21.476ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.605s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	53.598s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	43.506s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	36.171s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.413s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	20.768s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.161s		0	3	0.00
		chip_rv_dm_lc_disabled	21.084m	32.321ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.742m	3.944ms	1	3	33.33
		chip_sw_aes_enc_jitter_en	37.800s	10.260us	0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.280m	3.531ms	2	3	66.67
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.960m	5.489ms	2	3	66.67
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.906m	5.269ms	2	3	66.67
		chip_sw_hmac_enc_jitter_en	46.464s		0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.368m	4.778ms	1	3	33.33
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.543m	3.638ms	1	3	33.33
		chip_sw_kmac_mode_kmac	6.087m	5.101ms	2	3	66.67
		chip_sw_kmac_mode_kmac_jitter_en	36.526s		0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.838m	10.280ms	0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	18.016s		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	36.400s	10.200us	0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.522m	5.767ms	1	3	33.33
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.957m	5.590ms	1	3	33.33
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	1.763m		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	1.763m		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	1.849m		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.049m	4.637ms	2	3	66.67
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	17.601s		0	3	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.838m	10.280ms	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	53.790s	10.120us	0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	2.578m		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	2.509m		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.595m	4.608ms	2	3	66.67
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.595m	4.608ms	2	3	66.67
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.595m	4.608ms	2	3	66.67
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	9.322m	6.200ms	2	3	66.67
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	1.939m		0	3	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	1.939m		0	3	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	2.084m		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	26.802s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	16.162s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	34.348m	17.063ms	70	100	70.00
		chip_sw_data_integrity_escalation	15.984s		0	6	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	18.016s		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	9.322m	6.200ms	2	3	66.67
		chip_sw_keymgr_dpe_key_derivation	7.838m	10.280ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	2.084m		0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	4.211m	5.037ms	2	3	66.67
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	9.322m	6.200ms	2	3	66.67
		chip_sw_keymgr_dpe_key_derivation	7.838m	10.280ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	2.084m		0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	4.211m	5.037ms	2	3	66.67
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	18.016s		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	17.758s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	14.871s		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.338s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.819s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.469s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.817s		0	3	0.00
		chip_sw_lc_ctrl_transition	18.016s		0	15	0.00
		chip_prim_tl_access	14.559m	21.476ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	14.559m	21.476ms	3	3	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	17.845s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	17.127s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.690s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	2.509m		0	3	0.00
		chip_sw_aes_enc_jitter_en	37.800s	10.260us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	46.464s		0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	53.790s	10.120us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	36.526s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	26.802s		0	3	0.00
		chip_sw_clkmgr_jitter	4.137m	3.688ms	2	3	66.67
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	9.372m	9.396ms	1	3	33.33
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	9.372m	9.396ms	1	3	33.33
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.373m	4.573ms	0	3	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	5.054m	4.564ms	0	3	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.540m	3.718ms	1	3	33.33
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.175m	4.912ms	0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.495m	6.266ms	1	3	33.33
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	5.275m	5.270ms	2	3	66.67
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.211m	5.037ms	2	3	66.67
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	31.238m	20.027ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	31.238m	20.027ms	0	3	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	4.083m	3.476ms	2	3	66.67
		chip_sw_aon_timer_smoketest	5.446m	5.024ms	2	3	66.67
		chip_sw_clkmgr_smoketest	4.439m	4.126ms	2	3	66.67
		chip_sw_csrng_smoketest	5.352m	4.830ms	2	3	66.67
		chip_sw_gpio_smoketest	5.982m	5.550ms	2	3	66.67
		chip_sw_hmac_smoketest	6.737m	5.369ms	2	3	66.67
		chip_sw_kmac_smoketest	5.655m	3.948ms	2	3	66.67
		chip_sw_otbn_smoketest	7.600m	5.896ms	2	3	66.67
		chip_sw_otp_ctrl_smoketest	4.310m	3.638ms	2	3	66.67
		chip_sw_rv_plic_smoketest	5.123m	4.398ms	2	3	66.67
		chip_sw_rv_timer_smoketest	6.693m	4.285ms	2	3	66.67
		chip_sw_rstmgr_smoketest	4.310m	4.883ms	1	3	33.33
		chip_sw_sram_ctrl_smoketest	3.893m	5.173ms	2	3	66.67
		chip_sw_uart_smoketest	4.007m	4.154ms	2	3	66.67
V2	chip_sw_rom_functests	rom_keymgr_functest	58.524s		0	3	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	59.088s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	16.587s		0	3	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	16.415s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	16.772s		0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	16.229s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	16.880s		0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	4.925m	5.770ms	1	3	33.33
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	18.944s		0	3	0.00
		chip_rv_dm_lc_disabled	21.084m	32.321ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	17.763s		0	3	0.00
		chip_sw_lc_walkthrough_prod	17.406s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	17.149s		0	3	0.00
		chip_sw_lc_walkthrough_rma	17.708s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	18.944s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	18.210s		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	21.933s		0	3	0.00
		rom_volatile_raw_unlock	16.160s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	57.538s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	17.041s		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	16.324s		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.688m	5.531ms	0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.688m	5.531ms	0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.900s		0	3	0.00
		chip_same_csr_outstanding	9.810s		0	3	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.900s		0	3	0.00
		chip_same_csr_outstanding	9.810s		0	3	0.00
V2	xbar_base_random_sequence	xbar_random	3.214m	534.008us	89	100	89.00
V2	xbar_random_delay	xbar_smoke_zero_delays	42.228s		82	100	82.00
		xbar_smoke_large_delays	6.016m	2.703ms	83	100	83.00
		xbar_smoke_slow_rsp	7.058m	2.079ms	76	100	76.00
		xbar_random_zero_delays	1.745m	73.389us	80	100	80.00
		xbar_random_large_delays	28.470m	14.139ms	80	100	80.00
		xbar_random_slow_rsp	40.627m	14.542ms	85	100	85.00
V2	xbar_unmapped_address	xbar_unmapped_addr	2.589m	234.267us	83	100	83.00
		xbar_error_and_unmapped_addr	1.781m	238.819us	82	100	82.00
V2	xbar_error_cases	xbar_error_random	3.217m	564.522us	84	100	84.00
		xbar_error_and_unmapped_addr	1.781m	238.819us	82	100	82.00
V2	xbar_all_access_same_device	xbar_access_same_device	5.712m	954.262us	81	100	81.00
		xbar_access_same_device_slow_rsp	58.971m	19.306ms	77	100	77.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	3.379m	463.190us	88	100	88.00
V2	xbar_stress_all	xbar_stress_all	31.751m	5.124ms	86	100	86.00
		xbar_stress_all_with_error	21.258m	2.917ms	87	100	87.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	55.819m	7.721ms	83	100	83.00
		xbar_stress_all_with_reset_error	51.216m	8.457ms	76	100	76.00
V2	rom_e2e_smoke	rom_e2e_smoke	16.557s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	16.203s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	16.073s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	15.266s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.215s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.709s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.798s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.479s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.794s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	13.815s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.489s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.285s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.321s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.521s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	16.805s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	17.887s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.170s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	17.583s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	18.300s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	17.301s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.817s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.150s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	16.474s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	15.844s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	15.433s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	15.590s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	14.897s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	13.185s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	11.688s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.293s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.223s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.522s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.806s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	17.161s		0	3	0.00
		rom_e2e_asm_init_dev	14.009s		0	3	0.00
		rom_e2e_asm_init_prod	17.261s		0	3	0.00
		rom_e2e_asm_init_prod_end	16.561s		0	3	0.00
		rom_e2e_asm_init_rma	16.662s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	16.188s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	15.829s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	15.768s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	16.025s		0	3	0.00
V2		TOTAL			1544	2429	63.57
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.043m	5.704ms	2	3	66.67
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.914m	5.273ms	1	3	33.33
V2S		TOTAL			3	6	50.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.339s		0	1	0.00
		rom_e2e_jtag_debug_dev	16.333s		0	1	0.00
		rom_e2e_jtag_debug_rma	16.734s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	16.886s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	34.348m	17.063ms	70	100	70.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	19.558s		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.305s		0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	17.052s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.977s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.339s		0	1	0.00
		rom_e2e_jtag_debug_dev	16.333s		0	1	0.00
		rom_e2e_jtag_debug_rma	16.734s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	16.051s		0	1	0.00
		rom_e2e_jtag_inject_dev	15.764s		0	1	0.00
		rom_e2e_jtag_inject_rma	16.393s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	52.073s		0	3	0.00
V3		TOTAL			0	20	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	24.978m	13.280ms	1	3	33.33
		chip_sw_entropy_src_kat_test	5.690m	4.671ms	1	3	33.33
		chip_sw_entropy_src_ast_rng_req	3.777m	3.594ms	2	3	66.67
		chip_plic_all_irqs_0	10.275m	7.343ms	2	3	66.67
		chip_plic_all_irqs_10	12.100m	6.991ms	2	3	66.67
		chip_sw_dma_inline_hashing	6.050m	5.264ms	2	3	66.67
		chip_sw_dma_abort	4.918m	5.046ms	0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	15.965s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	15.275s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	18.052s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	16.341s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	17.637s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	15.169s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	15.518s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	57.836s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	16.461s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	58.038s		0	3	0.00
		chip_sw_entropy_src_smoketest	5.518m	5.794ms	1	3	33.33
		chip_sw_mbx_smoketest	6.208m	5.975ms	2	3	66.67
		TOTAL			1640	2668	61.47

Failure Buckets

• Job returned non-zero exit code has 847 failures:

  • Test chip_sw_example_rom has 3 failures.

    • 0.chip_sw_example_rom.31460581683645211365300846247444819193904107745883649939101459508066444365659
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp8232850304627425222/platforms-0.0.11.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp8232850304627425222/platforms-0.0.11.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp8232850304627425222/platforms-0.0.11.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: /nightly/current_run/opentitan/sw/device/tests/BUILD:1756:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
        ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted
        INFO: Elapsed time: 9.751s, Critical Path: 0.74s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_example_rom.62563657821793867891423028021466751744973184863293032146863850500159987872758
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log

            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust+/rust/private/repository_utils.bzl", line 813, column 42, in load_arbitrary_tool
                result = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://static.rust-lang.org/dist/2025-01-03/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools/temp5725462028069474643/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz: Unknown host: static.rust-lang.org
        ERROR: no such package '@@rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools//': java.io.IOException: Error downloading [https://static.rust-lang.org/dist/2025-01-03/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools/temp5725462028069474643/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz: Unknown host: static.rust-lang.org
        ERROR: /nightly/current_run/opentitan/sw/host/opentitantool/BUILD:10:12: //sw/host/opentitantool:opentitantool depends on @@rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools//:rust_toolchain in repository @@rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools which failed to fetch. no such package '@@rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools//': java.io.IOException: Error downloading [https://static.rust-lang.org/dist/2025-01-03/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools/temp5725462028069474643/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz: Unknown host: static.rust-lang.org
        ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Analysis failed
        INFO: Elapsed time: 3.638s, Critical Path: 0.02s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test chip_sw_example_manufacturer has 3 failures.

    • 0.chip_sw_example_manufacturer.37668887100082273155893949389807769577304660466912906529982948705791307484791
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp11947711833373824853/platforms-0.0.11.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp11947711833373824853/platforms-0.0.11.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp11947711833373824853/platforms-0.0.11.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/+hooks+manufacturer_test_hooks/BUILD.bazel:143:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
        ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted
        INFO: Elapsed time: 1.918s, Critical Path: 0.04s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_example_manufacturer.29197465578709600209921046146985326448206040285200760376800177116974067710947
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

        Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 0.104s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test chip_sw_example_concurrency has 2 failures.

    • 0.chip_sw_example_concurrency.15834298356726209990251647864751894818428104550889641840745284745612172798436
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp14478080970280108266/platforms-0.0.11.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp14478080970280108266/platforms-0.0.11.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp14478080970280108266/platforms-0.0.11.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: /nightly/current_run/opentitan/sw/device/tests/BUILD:1701:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
        ERROR: Analysis of target '//sw/device/tests:example_concurrency_test_sim_dv' failed; build aborted
        INFO: Elapsed time: 1.732s, Critical Path: 0.05s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_example_concurrency.82740687422356439365397377597116251157258461452668652778636635593568257487614
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_concurrency/latest/run.log

                result = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://static.rust-lang.org/dist/2025-01-03/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools/temp6354721594066961514/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz: Unknown host: static.rust-lang.org
        ERROR: no such package '@@rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools//': java.io.IOException: Error downloading [https://static.rust-lang.org/dist/2025-01-03/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools/temp6354721594066961514/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz: Unknown host: static.rust-lang.org
        ERROR: /nightly/current_run/opentitan/sw/host/opentitantool/BUILD:10:12: //sw/host/opentitantool:opentitantool depends on @@rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools//:rust_toolchain in repository @@rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools which failed to fetch. no such package '@@rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools//': java.io.IOException: Error downloading [https://static.rust-lang.org/dist/2025-01-03/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools/temp6354721594066961514/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz: Unknown host: static.rust-lang.org
        ERROR: Analysis of target '//sw/device/tests:example_concurrency_test_sim_dv' failed; build aborted: Analysis failed
        INFO: Elapsed time: 5.581s, Critical Path: 0.03s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        FAILED:
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • Test chip_sw_all_escalation_resets has 14 failures.

    • 0.chip_sw_all_escalation_resets.111011415435214668771258465979119723405053630041874936518026637072857390764568
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log

                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp6885531905317334882/platforms-0.0.11.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp6885531905317334882/platforms-0.0.11.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp6885531905317334882/platforms-0.0.11.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD:303:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
        ERROR: Analysis of target '//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv' failed; build aborted
        INFO: Elapsed time: 0.186s, Critical Path: 0.04s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_all_escalation_resets.93929702771560254567028427283763502532785828299557557409332233276056023399165
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest/run.log

                result = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://static.rust-lang.org/dist/2025-01-03/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools/temp9772839585854992417/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz: Unknown host: static.rust-lang.org
        ERROR: no such package '@@rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools//': java.io.IOException: Error downloading [https://static.rust-lang.org/dist/2025-01-03/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools/temp9772839585854992417/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz: Unknown host: static.rust-lang.org
        ERROR: /nightly/current_run/opentitan/sw/host/opentitantool/BUILD:10:12: //sw/host/opentitantool:opentitantool depends on @@rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools//:rust_toolchain in repository @@rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools which failed to fetch. no such package '@@rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools//': java.io.IOException: Error downloading [https://static.rust-lang.org/dist/2025-01-03/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools/temp9772839585854992417/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz: Unknown host: static.rust-lang.org
        ERROR: Analysis of target '//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv' failed; build aborted: Analysis failed
        INFO: Elapsed time: 4.532s, Critical Path: 0.69s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        FAILED:
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 12 more failures.

  • Test chip_sw_rstmgr_rst_cnsty_escalation has 2 failures.

    • 0.chip_sw_rstmgr_rst_cnsty_escalation.59745518192952212531230920226474245618976542171163910707434229702757548926058
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

                download_info = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp11196731744557223609/platforms-0.0.11.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp11196731744557223609/platforms-0.0.11.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/bazel_tools/tools/BUILD:5:6: @@bazel_tools//tools:host_platform depends on @@platforms//host:host in repository @@platforms which failed to fetch. no such package '@@platforms//host': java.io.IOException: Error downloading [https://github.com/bazelbuild/platforms/releases/download/0.0.11/platforms-0.0.11.tar.gz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/platforms/temp11196731744557223609/platforms-0.0.11.tar.gz: Unknown host: release-assets.githubusercontent.com
        ERROR: /nightly/current_run/opentitan/sw/device/tests/sim_dv/BUILD:303:15: Target @@bazel_tools//tools:host_platform was referenced as a platform, but does not provide PlatformInfo
        ERROR: Analysis of target '//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv' failed; build aborted
        INFO: Elapsed time: 0.140s, Critical Path: 0.04s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_rstmgr_rst_cnsty_escalation.59243860131501038675388723014056779566932821797340678606538984904229596438162
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

            File "/nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust+/rust/private/repository_utils.bzl", line 813, column 42, in load_arbitrary_tool
                result = ctx.download_and_extract(
        Error in download_and_extract: java.io.IOException: Error downloading [https://static.rust-lang.org/dist/2025-01-03/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools/temp10216272921596248662/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz: Unknown host: static.rust-lang.org
        ERROR: no such package '@@rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools//': java.io.IOException: Error downloading [https://static.rust-lang.org/dist/2025-01-03/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools/temp10216272921596248662/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz: Unknown host: static.rust-lang.org
        ERROR: /nightly/current_run/opentitan/sw/host/opentitantool/BUILD:10:12: //sw/host/opentitantool:opentitantool depends on @@rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools//:rust_toolchain in repository @@rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools which failed to fetch. no such package '@@rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools//': java.io.IOException: Error downloading [https://static.rust-lang.org/dist/2025-01-03/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz] to /nightly/runs/.cache/bazel/_bazel_root/5fbabd58f74ed10ce4d4abef6fdbdfee/external/rules_rust++rust+rust_host__x86_64-unknown-linux-gnu__nightly_tools/temp10216272921596248662/rustc-nightly-x86_64-unknown-linux-gnu.tar.xz: Unknown host: static.rust-lang.org
        ERROR: Analysis of target '//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv' failed; build aborted: Analysis failed
        INFO: Elapsed time: 4.991s, Critical Path: 0.02s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

  • ... and 239 more tests.

• Job timed out after * minutes has 74 failures:

  • Test chip_sw_kmac_mode_cshake has 1 failures.

    • 1.chip_sw_kmac_mode_cshake.40005519085562054428434934076427486443080923247596708758093032055704169877009
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_cshake/latest/run.log

        Job timed out after 60 minutes
      

  • Test xbar_stress_all_with_error has 2 failures.

    • 1.xbar_stress_all_with_error.3377031614556223929763718195983948382660501877362097961938943534023344923820
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.xbar_stress_all_with_error/latest/run.log

        Job timed out after 60 minutes
      

    • 95.xbar_stress_all_with_error.10182366649991089350620933913059487330531233768103207117363589559007549752620
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/95.xbar_stress_all_with_error/latest/run.log

        Job timed out after 60 minutes
      

  • Test chip_sw_all_escalation_resets has 2 failures.

    • 2.chip_sw_all_escalation_resets.49396756689703953378758020682889163793592494515299487573994850888423597454382
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/run.log

        Job timed out after 60 minutes
      

    • 93.chip_sw_all_escalation_resets.57007539174947107260181460079659719789383834977181735296143729152710202376272
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/93.chip_sw_all_escalation_resets/latest/run.log

        Job timed out after 60 minutes
      

  • Test chip_sw_sram_ctrl_scrambled_access has 1 failures.

    • 2.chip_sw_sram_ctrl_scrambled_access.72415384677831387521082599162851814351157566004010274514659973384087037352455
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_sram_ctrl_scrambled_access/latest/run.log

        Job timed out after 60 minutes
      

  • Test xbar_stress_all_with_reset_error has 5 failures.

    • 3.xbar_stress_all_with_reset_error.84722497040394376417557490073515362604047397624149124235426172585978729122692
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_stress_all_with_reset_error/latest/run.log

        Job timed out after 60 minutes
      

    • 38.xbar_stress_all_with_reset_error.6916221327352602278717900626097439938659841480098708607395440765464320609260
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/38.xbar_stress_all_with_reset_error/latest/run.log

        Job timed out after 60 minutes
      

    • ... and 3 more failures.

  • ... and 16 more tests.

• Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 29 failures:

  • Test chip_tl_errors has 29 failures.

    • 0.chip_tl_errors.26770088853040499934429963812567047679093131449242397436742776901828410532726
      Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

            Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
        UVM_ERROR @ 4784.508600 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
        UVM_INFO @ 4784.508600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_tl_errors.51967031177586171636157848086623590091184236179692939575074894352458503749078
      Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log

            Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
        UVM_ERROR @ 4254.365595 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
        UVM_INFO @ 4254.365595 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 27 more failures.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 14 failures:

  • Test chip_sw_aes_enc_jitter_en has 2 failures.

    • 1.chip_sw_aes_enc_jitter_en.25413633670102391436884407475874072480560818315143701704972367925648730282074
      Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.chip_sw_aes_enc_jitter_en.54398644577059353925324631842352932585834136507942864493350111655061499868575
      Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_hmac_enc_jitter_en has 1 failures.

    • 1.chip_sw_hmac_enc_jitter_en.8592187821821467691545852877198894377417603202967496814534513344061057414157
      Line 528, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 2 failures.

    • 1.chip_sw_keymgr_dpe_key_derivation_jitter_en.25457536596283007122663614701542001923843474694769456450258462428135111761794
      Line 507, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log

        UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.chip_sw_keymgr_dpe_key_derivation_jitter_en.31274812896096959747452115839099662082451791644910362699349514526725860135693
      Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log

        UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.

    • 1.chip_sw_kmac_mode_kmac_jitter_en.50189936876150094124325245469373836604746876078727451543092848128688954757417
      Line 412, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log

        UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_aes_enc_jitter_en_reduced_freq has 2 failures.

    • 1.chip_sw_aes_enc_jitter_en_reduced_freq.14211661129107681603065259879705251767910538716456467250340745075275731119557
      Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log

        UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.chip_sw_aes_enc_jitter_en_reduced_freq.4463076625156034708420634723481685513774195449232998705114268654207065224113
      Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log

        UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 4 more tests.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:

  • Test chip_csr_bit_bash has 3 failures.

    • 0.chip_csr_bit_bash.98133252241004170856520927804407269214313789827398814586937324764409001497847
      Line 143, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_csr_bit_bash.87919416145085793110676027750629261889574002716776251781183834570826613880634
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_csr_aliasing has 3 failures.

    • 0.chip_csr_aliasing.4212808774994068848318029576637855942064817498181938137126940641998716382856
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_csr_aliasing.73345186127864622219437950724323016315477858965282377300196338124380411345453
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_same_csr_outstanding has 3 failures.

    • 0.chip_same_csr_outstanding.109173940029236606748990858769718009614014670940811746685593654237556471081638
      Line 143, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_same_csr_outstanding.103179056084138436783325734695170653833923245396637171969586832210272141531608
      Line 143, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Error-[CNST-CIF] Constraints inconsistency failure has 7 failures:

  • Test chip_padctrl_attributes has 7 failures.

    • 0.chip_padctrl_attributes.62834327783846766938876492939610237111518691497837076490593692141442616720657
      Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.
      

    • 1.chip_padctrl_attributes.8476603251180556280967422832035575364150632837094347339838068023155304601542
      Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.
      

    • ... and 5 more failures.

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 7 failures:

  • Test chip_sw_aon_timer_irq has 2 failures.

    • 1.chip_sw_aon_timer_irq.96900422894946991065180774272814108508056200794373749262371318871787763593676
      Line 491, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log

        UVM_ERROR @ 18018.670674 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
      
        UVM_INFO @ 18018.670674 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.chip_sw_aon_timer_irq.115644389075454703270788720427775069781084537870511220080537043935465471057845
      Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_irq/latest/run.log

        UVM_ERROR @ 18026.746759 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
      
        UVM_INFO @ 18026.746759 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 4 failures.

    • 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.78147290424239408479198160707306441816355076983488769715339895630613024849359
      Line 491, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

        UVM_ERROR @ 18018.556235 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
      
        UVM_INFO @ 18018.556235 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.85267194621033151470100182621960325269632442148651283677843967675427690829092
      Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

        UVM_ERROR @ 18018.648077 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
      
        UVM_INFO @ 18018.648077 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

  • Test chip_sw_rstmgr_cpu_info has 1 failures.

    • 2.chip_sw_rstmgr_cpu_info.107168031945924626458300137961381371954140407571619031678650600551545833371055
      Line 420, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest/run.log

        UVM_ERROR @ 20026.682847 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns
      
        UVM_INFO @ 20026.682847 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 6 failures:

  • Test chip_sw_clkmgr_off_aes_trans has 2 failures.

    • 1.chip_sw_clkmgr_off_aes_trans.7242403604440575307348553360382981676774115951122483062764875733595282382502
      Line 488, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log

        UVM_ERROR @ 12026.805468 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12026.805468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.chip_sw_clkmgr_off_aes_trans.18898381065775569138761152030007894095347565036456816181226222044035799592297
      Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_aes_trans/latest/run.log

        UVM_ERROR @ 12026.923434 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12026.923434 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

    • 1.chip_sw_clkmgr_off_hmac_trans.7150562229027185321523634588632425745523085432915806290741129585695789772178
      Line 481, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log

        UVM_ERROR @ 12026.602559 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12026.602559 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_clkmgr_off_kmac_trans has 2 failures.

    • 1.chip_sw_clkmgr_off_kmac_trans.105296366690864547668360711952002300610669914861023034897293088598227267292110
      Line 457, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log

        UVM_ERROR @ 12018.548799 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12018.548799 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.chip_sw_clkmgr_off_kmac_trans.97753004169468097119293811661250610017499673631692855358889702824053747252510
      Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_kmac_trans/latest/run.log

        UVM_ERROR @ 12027.012914 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12027.012914 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

    • 1.chip_sw_clkmgr_off_otbn_trans.82718364931410314263233703692069808403554599219543194455548668632967987891967
      Line 435, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest/run.log

        UVM_ERROR @ 12026.703951 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12026.703951 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 6 failures:

  • Test chip_sw_all_escalation_resets has 6 failures.

    • 8.chip_sw_all_escalation_resets.99932744515795906865479611055202250540851793240176147528775826649816990551648
      Line 379, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest/run.log

        UVM_FATAL @  10.340001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
        UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 22.chip_sw_all_escalation_resets.45428379519749776273968656734473941508279746394261278441572600938540784356002
      Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest/run.log

        UVM_FATAL @  10.380001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
        UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47282) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 5 failures:

  • Test chip_jtag_csr_rw has 3 failures.

    • 0.chip_jtag_csr_rw.40487752966061494970298426236242651754906676320502659671474724120788233436607
      Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

        UVM_ERROR @ 5467.711893 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47282) { a_addr: 'h30480000  a_data: 'hcf101f4a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2e  a_opcode: 'h1  a_user: 'h248f4  d_param: 'h0  d_source: 'h2e  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 5467.711893 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_jtag_csr_rw.47666082361516978895673031205003613414576029921287089644497491887136862730857
      Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log

        UVM_ERROR @ 5236.999547 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47282) { a_addr: 'h30480000  a_data: 'he458200f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3c  a_opcode: 'h0  a_user: 'h2695d  d_param: 'h0  d_source: 'h3c  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 5236.999547 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_jtag_mem_access has 2 failures.

    • 1.chip_jtag_mem_access.97500473906971406764833877651184730181393938122156708399816288893035153756440
      Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log

        UVM_ERROR @ 4866.405348 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47282) { a_addr: 'h30480000  a_data: 'hfff677d8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h11  a_opcode: 'h1  a_user: 'h248a3  d_param: 'h0  d_source: 'h11  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 4866.405348 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.chip_jtag_mem_access.72366739546846851885169339747541329334278179545081717337052547945505564109075
      Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_jtag_mem_access/latest/run.log

        UVM_ERROR @ 4584.247638 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47282) { a_addr: 'h30480000  a_data: 'hb1a10da2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h19  a_opcode: 'h1  a_user: 'h2489b  d_param: 'h0  d_source: 'h19  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 4584.247638 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 4 failures:

  • Test chip_sw_keymgr_dpe_key_derivation has 2 failures.

    • 1.chip_sw_keymgr_dpe_key_derivation.72090604167567593912853576489316071414098283485427177460160915779350746787543
      Line 505, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log

        UVM_ERROR @ 10280.070085 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (8253635994269904753490081162948265487734455429510895412622512917037562475967206679375528054282006375401257432467113887832602897619953962356950286505172060 [0x9d96eeafaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd31bc05e5e7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 10280.070085 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.chip_sw_keymgr_dpe_key_derivation.62574922875897967438910222378597141319787687472027212538111117599755090595609
      Line 411, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_keymgr_dpe_key_derivation/latest/run.log

        UVM_ERROR @ 8449.023880 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (1528092926828667082452995061787654388284057317754234376610043005400721281014220525670540139812794528338339703440679658735785363728481641652741574597368924 [0x1d2d29a2aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd39b7b99537f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 8449.023880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_keymgr_dpe_key_derivation_prod has 2 failures.

    • 1.chip_sw_keymgr_dpe_key_derivation_prod.78862484845198816443897444777897710912257483925713507933744596672694252617980
      Line 485, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

        UVM_ERROR @ 6518.696041 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11750169082403183037458691562787174354518352875339315489360197695396381217000112571115779588253421846068500656758891917789318362640203105328647299098041436 [0xe059a14daae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3660f11bc7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 6518.696041 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.chip_sw_keymgr_dpe_key_derivation_prod.31488048067077222445667363105597166906872285451129031009404835156492979666960
      Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

        UVM_ERROR @ 9059.617420 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11750169082403183037458691562787174354518352875339315489360197695396381217000112571115779588253421846068500656758891917789318362640203105328647299098041436 [0xe059a14daae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3660f11bc7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 9059.617420 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_vseq.sv:594) virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault has 3 failures:

  • Test chip_sw_all_escalation_resets has 3 failures.

    • 7.chip_sw_all_escalation_resets.101036960205024814346827845401851380998340693618431150531018396383672451873070
      Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 4188.984754 us: (cip_base_vseq.sv:594) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
        UVM_INFO @ 4188.984754 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 32.chip_sw_all_escalation_resets.50461901719252871229934052284475540311939007115480243373992029063929912810006
      Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/32.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 5496.083088 us: (cip_base_vseq.sv:594) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
        UVM_INFO @ 5496.083088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:

  • Test chip_sw_all_escalation_resets has 3 failures.

    • 14.chip_sw_all_escalation_resets.102848200102759816548279832437471877336360972510116909574481711163595919738652
      Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/14.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 3872.152541 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
        UVM_INFO @ 3872.152541 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 25.chip_sw_all_escalation_resets.94366040618519692021490080906739213133892383257030120031105241227649847109180
      Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/25.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 3965.868820 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
        UVM_INFO @ 3965.868820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 2 failures:

  • Test chip_sw_kmac_app_rom has 2 failures.

    • 1.chip_sw_kmac_app_rom.28814017805418019209844707969726034023877494427822429969052845590535940008096
      Line 498, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log

        UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
        UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.chip_sw_kmac_app_rom.83853457595467225324578791300201286980672303329095925671893795761982814085218
      Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_kmac_app_rom/latest/run.log

        UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
        UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 2 failures:

  • Test chip_rv_dm_ndm_reset_req has 2 failures.

    • 1.chip_rv_dm_ndm_reset_req.28118918034710508623432393375910200713226204794386151136960089115350152551686
      Line 373, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest/run.log

        UVM_FATAL @ 13242.684124 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
        UVM_INFO @ 13242.684124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.chip_rv_dm_ndm_reset_req.25520807035194384052004563513432966075795042568823660791774108255528603381032
      Line 372, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_rv_dm_ndm_reset_req/latest/run.log

        UVM_FATAL @ 14297.350750 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
        UVM_INFO @ 14297.350750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 2 failures:

  • Test chip_sw_dma_abort has 2 failures.

    • 1.chip_sw_dma_abort.66860858652600623634917534617629842800688710053600742672996290669317518151711
      Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log

        UVM_FATAL @ 4338.789010 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
        UVM_INFO @ 4338.789010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.chip_sw_dma_abort.43010976603316607139920616653839763348712967576123627535239195624428090172020
      Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_dma_abort/latest/run.log

        UVM_FATAL @ 5045.800530 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
        UVM_INFO @ 5045.800530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 2 failures:

  • Test chip_sw_all_escalation_resets has 2 failures.

    • 62.chip_sw_all_escalation_resets.11777299666038919242152546134715313592084170936890179789248784416294159787529
      Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/62.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 12018.659496 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12018.659496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 77.chip_sw_all_escalation_resets.66584224226139820565027325725477381959164788603789867626195436212147064605164
      Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/77.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 12018.540961 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12018.540961 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:

  • Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.

    • 1.chip_sw_rv_core_ibex_nmi_irq.9819426285430434169210068289430877875646040837070120071610010547052374076258
      Line 1490, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log

        UVM_ERROR @ 4912.243865 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
        UVM_INFO @ 4912.243865 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:

  • Test chip_sw_spi_device_pass_through_collision has 1 failures.

    • 2.chip_sw_spi_device_pass_through_collision.31631055864580690647773878394343357715409962910266286287572168088304098438336
      Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest/run.log

        UVM_ERROR @ 4066.158692 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
        UVM_INFO @ 4066.158692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:

  • Test chip_sw_rstmgr_alert_info has 1 failures.

    • 2.chip_sw_rstmgr_alert_info.63895589406130062493509577448308780200468846614019545236349508386779782783784
      Line 626, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_alert_info/latest/run.log

        UVM_ERROR @ 6528.417528 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
        UVM_INFO @ 6528.417528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:

  • Test chip_sw_soc_proxy_external_alerts has 1 failures.

    • 2.chip_sw_soc_proxy_external_alerts.98582832852844472914193203696284323093645647950031377010235717269695214855381
      Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_external_alerts/latest/run.log

        UVM_ERROR @ 4572.703592 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
        UVM_INFO @ 4572.703592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:

  • Test chip_sw_soc_proxy_external_wakeup has 1 failures.

    • 2.chip_sw_soc_proxy_external_wakeup.109000032858557926325000465174101408787503094828044474043349926735101514610850
      Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_soc_proxy_external_wakeup/latest/run.log

        UVM_ERROR @ 4563.822872 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
        UVM_INFO @ 4563.822872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:

  • Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.

    • 2.chip_sw_aon_timer_wdog_bite_reset.60048786118970731631381507976728928155167248874057020163223894360667993805473
      Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest/run.log

        UVM_ERROR @ 4726.218220 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
        UVM_INFO @ 4726.218220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * has 1 failures:

  • Test chip_sw_rv_core_ibex_rnd has 1 failures.

    • 2.chip_sw_rv_core_ibex_rnd.2323929352804665166867380683838444374246470202330250723801908377410684672841
      Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rv_core_ibex_rnd/latest/run.log

        UVM_ERROR @ 5565.162500 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
        UVM_INFO @ 5565.162500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---