AES/MASKED Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	67.368us	1	1	100.00
V1	smoke	aes_smoke	13.000s	643.903us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	88.932us	5	5	100.00
V1	csr_rw	aes_csr_rw	2.000s	70.610us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	2.796ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	104.462us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	108.180us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	70.610us	20	20	100.00
		aes_csr_aliasing	3.000s	104.462us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	643.903us	50	50	100.00
		aes_config_error	5.000s	90.027us	50	50	100.00
		aes_stress	14.000s	1.830ms	50	50	100.00
V2	key_length	aes_smoke	13.000s	643.903us	50	50	100.00
		aes_config_error	5.000s	90.027us	50	50	100.00
		aes_stress	14.000s	1.830ms	50	50	100.00
V2	back2back	aes_stress	14.000s	1.830ms	50	50	100.00
		aes_b2b	25.000s	457.619us	50	50	100.00
V2	backpressure	aes_stress	14.000s	1.830ms	50	50	100.00
V2	multi_message	aes_smoke	13.000s	643.903us	50	50	100.00
		aes_config_error	5.000s	90.027us	50	50	100.00
		aes_stress	14.000s	1.830ms	50	50	100.00
		aes_alert_reset	1.217m	4.420ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	7.000s	391.818us	50	50	100.00
		aes_config_error	5.000s	90.027us	50	50	100.00
		aes_alert_reset	1.217m	4.420ms	50	50	100.00
V2	trigger_clear_test	aes_clear	40.000s	2.191ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	400.468us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.217m	4.420ms	50	50	100.00
V2	stress	aes_stress	14.000s	1.830ms	50	50	100.00
V2	sideload	aes_stress	14.000s	1.830ms	50	50	100.00
		aes_sideload	5.000s	85.564us	50	50	100.00
V2	deinitialization	aes_deinit	10.000s	571.515us	50	50	100.00
V2	stress_all	aes_stress_all	2.083m	6.013ms	9	10	90.00
V2	alert_test	aes_alert_test	3.000s	54.446us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	3.000s	122.345us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	3.000s	122.345us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	88.932us	5	5	100.00
		aes_csr_rw	2.000s	70.610us	20	20	100.00
		aes_csr_aliasing	3.000s	104.462us	5	5	100.00
		aes_same_csr_outstanding	3.000s	215.091us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	88.932us	5	5	100.00
		aes_csr_rw	2.000s	70.610us	20	20	100.00
		aes_csr_aliasing	3.000s	104.462us	5	5	100.00
		aes_same_csr_outstanding	3.000s	215.091us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	1.467m	3.851ms	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	729.830us	50	50	100.00
		aes_control_fi	1.000m	10.005ms	277	300	92.33
		aes_cipher_fi	57.000s	10.003ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	116.160us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	116.160us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	116.160us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	116.160us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	443.315us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	632.821us	5	5	100.00
		aes_tl_intg_err	3.000s	267.597us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	267.597us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.217m	4.420ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	116.160us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	643.903us	50	50	100.00
		aes_stress	14.000s	1.830ms	50	50	100.00
		aes_alert_reset	1.217m	4.420ms	50	50	100.00
		aes_core_fi	34.000s	10.007ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	116.160us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	181.811us	50	50	100.00
		aes_stress	14.000s	1.830ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	14.000s	1.830ms	50	50	100.00
		aes_sideload	5.000s	85.564us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	181.811us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	181.811us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	181.811us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	181.811us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	181.811us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	14.000s	1.830ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	14.000s	1.830ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	729.830us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	729.830us	50	50	100.00
		aes_control_fi	1.000m	10.005ms	277	300	92.33
		aes_cipher_fi	57.000s	10.003ms	341	350	97.43
		aes_ctr_fi	3.000s	78.126us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	729.830us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	729.830us	50	50	100.00
		aes_control_fi	1.000m	10.005ms	277	300	92.33
		aes_cipher_fi	57.000s	10.003ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	57.000s	10.003ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	729.830us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	729.830us	50	50	100.00
		aes_control_fi	1.000m	10.005ms	277	300	92.33
		aes_ctr_fi	3.000s	78.126us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	729.830us	50	50	100.00
		aes_control_fi	1.000m	10.005ms	277	300	92.33
		aes_cipher_fi	57.000s	10.003ms	341	350	97.43
		aes_ctr_fi	3.000s	78.126us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.217m	4.420ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	729.830us	50	50	100.00
		aes_control_fi	1.000m	10.005ms	277	300	92.33
		aes_cipher_fi	57.000s	10.003ms	341	350	97.43
		aes_ctr_fi	3.000s	78.126us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	729.830us	50	50	100.00
		aes_control_fi	1.000m	10.005ms	277	300	92.33
		aes_cipher_fi	57.000s	10.003ms	341	350	97.43
		aes_ctr_fi	3.000s	78.126us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	729.830us	50	50	100.00
		aes_control_fi	1.000m	10.005ms	277	300	92.33
		aes_ctr_fi	3.000s	78.126us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	729.830us	50	50	100.00
		aes_control_fi	1.000m	10.005ms	277	300	92.33
		aes_cipher_fi	57.000s	10.003ms	341	350	97.43
V2S		TOTAL			950	985	96.45
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	20.000s	412.899us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1556	1602	97.13

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.38	98.64	96.54	99.45	95.43	98.07	100.00	98.51	98.19

Failure Buckets

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 14 failures:
- Test aes_control_fi has 14 failures.
  - 41.aes_control_fi.39441796174437294386400140914208950560491736763576335238338981452019202480788
    Line 149, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/41.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10028358183 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10028358183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 54.aes_control_fi.73072301290597915929637424469117016521920237347917132147350540430105968473116
    Line 143, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/54.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009456534 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009456534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.
Job timed out after * minutes has 9 failures:
- Test aes_control_fi has 9 failures.
  - 6.aes_control_fi.63267118097770122195785115627235167813975701290549748247552258655324735644505
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 7.aes_control_fi.10313592653023734751087558883459118057534427286174365584074368745434016295012
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 7 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 11.aes_cipher_fi.6576448893797824890258692109021949526746751987349608106716878172037551424865
    Line 131, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007816076 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007816076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 63.aes_cipher_fi.84002045489818938393921400566585922147239006659675779549571432066486284617663
    Line 140, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/63.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008076210 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008076210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.25405510668555887304035931746539750772734305954179938156482849510974381387642
Line 598, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 441040545 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 441040545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.88575559027841690484189878436174002135563882584461637495758941103500466602679
Line 370, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 164720887 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 164720887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 23.aes_core_fi.15135521981238323667329191840246837178131475698657029877440148521344061097822
    Line 135, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/23.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010967686 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010967686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 36.aes_core_fi.39600862084167457148913575112166159597203435235031539373185979327852224356663
    Line 140, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/36.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10041135158 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10041135158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 4.aes_stress_all_with_rand_reset.73028851062713074391372110462855752754952250607866819488945316266302627061237
    Line 576, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 381108036 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 381108036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.aes_stress_all_with_rand_reset.102215223063210682882943057554667192069941757715265191666574902740322719239588
    Line 667, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2439922971 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2439922971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 5.aes_stress_all_with_rand_reset.62421144911074728733982904833966100953270134986394022941465003388070833260602
    Line 157, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 106989714 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 106989714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.24305049651881295467295291186193301812958859107740326834823669513766760026214
    Line 160, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  44325782 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  44325782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

0.aes_stress_all.870675569986579581577452054546834910769940240579473550927601651134433980767
Line 166507, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 889251659 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 889230826 PS)
  UVM_ERROR @ 889251659 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 889251659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.79276464497955995161612109673978451640502702247590665774726573535314873527098
    Line 145, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  14858421 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  14858421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.77829517636030044441571897751515008447518345024142954375975354223435778894063
    Line 200, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1241116370 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1241116370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```