AES/UNMASKED Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	67.939us	1	1	100.00
V1	smoke	aes_smoke	3.000s	63.201us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	68.728us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	55.527us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	523.609us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	70.962us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	94.350us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	55.527us	20	20	100.00
		aes_csr_aliasing	6.000s	70.962us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	3.000s	63.201us	50	50	100.00
		aes_config_error	3.000s	116.598us	50	50	100.00
		aes_stress	4.000s	125.141us	50	50	100.00
V2	key_length	aes_smoke	3.000s	63.201us	50	50	100.00
		aes_config_error	3.000s	116.598us	50	50	100.00
		aes_stress	4.000s	125.141us	50	50	100.00
V2	back2back	aes_stress	4.000s	125.141us	50	50	100.00
		aes_b2b	7.000s	411.231us	50	50	100.00
V2	backpressure	aes_stress	4.000s	125.141us	50	50	100.00
V2	multi_message	aes_smoke	3.000s	63.201us	50	50	100.00
		aes_config_error	3.000s	116.598us	50	50	100.00
		aes_stress	4.000s	125.141us	50	50	100.00
		aes_alert_reset	5.000s	271.929us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	209.021us	50	50	100.00
		aes_config_error	3.000s	116.598us	50	50	100.00
		aes_alert_reset	5.000s	271.929us	50	50	100.00
V2	trigger_clear_test	aes_clear	4.000s	829.517us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	4.000s	203.330us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	271.929us	50	50	100.00
V2	stress	aes_stress	4.000s	125.141us	50	50	100.00
V2	sideload	aes_stress	4.000s	125.141us	50	50	100.00
		aes_sideload	7.000s	341.308us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	1.037ms	50	50	100.00
V2	stress_all	aes_stress_all	25.000s	2.931ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	61.154us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	129.671us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	129.671us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	68.728us	5	5	100.00
		aes_csr_rw	6.000s	55.527us	20	20	100.00
		aes_csr_aliasing	6.000s	70.962us	5	5	100.00
		aes_same_csr_outstanding	6.000s	57.138us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	68.728us	5	5	100.00
		aes_csr_rw	6.000s	55.527us	20	20	100.00
		aes_csr_aliasing	6.000s	70.962us	5	5	100.00
		aes_same_csr_outstanding	6.000s	57.138us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	4.000s	212.415us	50	50	100.00
V2S	fault_inject	aes_fi	3.000s	242.560us	48	50	96.00
		aes_control_fi	57.000s	200.000ms	285	300	95.00
		aes_cipher_fi	31.000s	10.011ms	324	350	92.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	129.205us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	129.205us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	129.205us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	129.205us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	171.720us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	3.120ms	5	5	100.00
		aes_tl_intg_err	7.000s	139.496us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	139.496us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	271.929us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	129.205us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	3.000s	63.201us	50	50	100.00
		aes_stress	4.000s	125.141us	50	50	100.00
		aes_alert_reset	5.000s	271.929us	50	50	100.00
		aes_core_fi	1.950m	10.025ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	129.205us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	277.625us	50	50	100.00
		aes_stress	4.000s	125.141us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	125.141us	50	50	100.00
		aes_sideload	7.000s	341.308us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	277.625us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	277.625us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	277.625us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	277.625us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	277.625us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	125.141us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	125.141us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.000s	242.560us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.000s	242.560us	48	50	96.00
		aes_control_fi	57.000s	200.000ms	285	300	95.00
		aes_cipher_fi	31.000s	10.011ms	324	350	92.57
		aes_ctr_fi	3.000s	60.706us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.000s	242.560us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.000s	242.560us	48	50	96.00
		aes_control_fi	57.000s	200.000ms	285	300	95.00
		aes_cipher_fi	31.000s	10.011ms	324	350	92.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	31.000s	10.011ms	324	350	92.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.000s	242.560us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.000s	242.560us	48	50	96.00
		aes_control_fi	57.000s	200.000ms	285	300	95.00
		aes_ctr_fi	3.000s	60.706us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.000s	242.560us	48	50	96.00
		aes_control_fi	57.000s	200.000ms	285	300	95.00
		aes_cipher_fi	31.000s	10.011ms	324	350	92.57
		aes_ctr_fi	3.000s	60.706us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	271.929us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.000s	242.560us	48	50	96.00
		aes_control_fi	57.000s	200.000ms	285	300	95.00
		aes_cipher_fi	31.000s	10.011ms	324	350	92.57
		aes_ctr_fi	3.000s	60.706us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.000s	242.560us	48	50	96.00
		aes_control_fi	57.000s	200.000ms	285	300	95.00
		aes_cipher_fi	31.000s	10.011ms	324	350	92.57
		aes_ctr_fi	3.000s	60.706us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.000s	242.560us	48	50	96.00
		aes_control_fi	57.000s	200.000ms	285	300	95.00
		aes_ctr_fi	3.000s	60.706us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.000s	242.560us	48	50	96.00
		aes_control_fi	57.000s	200.000ms	285	300	95.00
		aes_cipher_fi	31.000s	10.011ms	324	350	92.57
V2S		TOTAL			937	985	95.13
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	11.000s	1.449ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1544	1602	96.38

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.10	97.53	94.54	98.63	93.06	98.07	93.33	98.08	97.99

Failure Buckets

Job timed out after * minutes has 22 failures:
- Test aes_control_fi has 7 failures.
  - 4.aes_control_fi.74881335192023697317143688619341227760830803022855806655595418701084912243378
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 22.aes_control_fi.42331513781012602471186378671804735538975807863167946671188794082183993140689
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 5 more failures.
- Test aes_cipher_fi has 15 failures.
  - 6.aes_cipher_fi.51873755661034351167412554852582276930193166947883519551720193457402375287155
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 14.aes_cipher_fi.101945224241081586884350463014030479307000577031135235477134732412782082375786
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 1.aes_cipher_fi.78292591142627296582131342797331660779428110177841984776348513449733301656759
    Line 145, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10021417025 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021417025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.aes_cipher_fi.12853812380258108286964848662704731323303056326603012870800848979790137290802
    Line 143, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004405105 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004405105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 32.aes_control_fi.8709173593716390049417943361531807626004725884152640537630775873620833892422
    Line 137, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009781440 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009781440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 45.aes_control_fi.46481642900149651932145318078976990820808255654568923732511288435458464201140
    Line 148, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/45.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10051842052 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10051842052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

2.aes_stress_all_with_rand_reset.59714408785503026768921527580767598022329543302740071658507160830098275917085
Line 266, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  83721236 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  83721236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.60035362069575731403674312593761414225162415351344612411593103790407211405079
Line 537, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 789106920 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 789106920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 1.aes_stress_all_with_rand_reset.2486128814436237839530870740646427272811886203289252346958358943210369626011
    Line 582, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1268498485 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1268498485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_stress_all_with_rand_reset.1873057854941365711925045650938786108970299717704557808569773368819344919962
    Line 168, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  96368242 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  96368242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 9.aes_core_fi.69844532466670395485751661868626112452481182407754368156799100112277829247317
    Line 143, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/9.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012978039 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012978039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 56.aes_core_fi.52955148154915188304129850637766030352497285390025956550247462373665813986781
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/56.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10018850863 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018850863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.110006908795383516627824810541300434560474419821985145900042028679493884693786
    Line 156, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 245257668 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 245257668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 8.aes_fi.41741259022036594789901235250839725384241447878506799910661252665070563009425
    Line 6612, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/8.aes_fi/latest/run.log
```
  UVM_FATAL @  17495928 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  17495928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

45.aes_fi.31390972618846024571257884664629366849260096255960701674030512982501346577444
Line 2990, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/45.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 8618665 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 8608665 PS)
  UVM_ERROR @   8618665 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @   8618665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 45.aes_core_fi.53758000528616239874041097688174709304474552289266600731176127298655554503806
    Line 134, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/45.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10034269379 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xed159484, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
  UVM_INFO @ 10034269379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 49.aes_core_fi.107557215332481909613520257124010810846247142171762332571677285877601750002252
    Line 135, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/49.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10024675603 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x66afb484, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
  UVM_INFO @ 10024675603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 53.aes_core_fi.652299690503277843350146056917009499529070004629060358845310207689486067206
    Line 135, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/53.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10043794731 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x69e95284, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10043794731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 81.aes_control_fi.111101517091586731137851376388075525718558883487263351417003051853569060123945
    Line 137, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/81.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```