CSRNG Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	7.000s	322.771us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	72.824us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	145.332us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	16.000s	1.143ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	278.828us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	8.000s	540.622us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	145.332us	20	20	100.00
		csrng_csr_aliasing	6.000s	278.828us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	27.000s	1.722ms	180	200	90.00
V2	alerts	csrng_alert	1.350m	6.392ms	500	500	100.00
V2	err	csrng_err	25.000s	33.419us	468	500	93.60
V2	cmds	csrng_cmds	10.467m	68.070ms	50	50	100.00
V2	life cycle	csrng_cmds	10.467m	68.070ms	50	50	100.00
V2	stress_all	csrng_stress_all	15.717m	72.013ms	48	50	96.00
V2	intr_test	csrng_intr_test	3.000s	49.814us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	281.270us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	25.000s	2.244ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	25.000s	2.244ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	72.824us	5	5	100.00
		csrng_csr_rw	4.000s	145.332us	20	20	100.00
		csrng_csr_aliasing	6.000s	278.828us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	501.480us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	72.824us	5	5	100.00
		csrng_csr_rw	4.000s	145.332us	20	20	100.00
		csrng_csr_aliasing	6.000s	278.828us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	501.480us	20	20	100.00
V2		TOTAL			1386	1440	96.25
V2S	tl_intg_err	csrng_sec_cm	6.000s	348.418us	5	5	100.00
		csrng_tl_intg_err	24.000s	1.111ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	154.688us	50	50	100.00
		csrng_csr_rw	4.000s	145.332us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.350m	6.392ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	15.717m	72.013ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	27.000s	1.722ms	180	200	90.00
		csrng_err	25.000s	33.419us	468	500	93.60
		csrng_sec_cm	6.000s	348.418us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	27.000s	1.722ms	180	200	90.00
		csrng_err	25.000s	33.419us	468	500	93.60
		csrng_sec_cm	6.000s	348.418us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	27.000s	1.722ms	180	200	90.00
		csrng_err	25.000s	33.419us	468	500	93.60
		csrng_sec_cm	6.000s	348.418us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	27.000s	1.722ms	180	200	90.00
		csrng_err	25.000s	33.419us	468	500	93.60
		csrng_sec_cm	6.000s	348.418us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	27.000s	1.722ms	180	200	90.00
		csrng_err	25.000s	33.419us	468	500	93.60
		csrng_sec_cm	6.000s	348.418us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	27.000s	1.722ms	180	200	90.00
		csrng_err	25.000s	33.419us	468	500	93.60
		csrng_sec_cm	6.000s	348.418us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	27.000s	1.722ms	180	200	90.00
		csrng_err	25.000s	33.419us	468	500	93.60
		csrng_sec_cm	6.000s	348.418us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.350m	6.392ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	27.000s	1.722ms	180	200	90.00
		csrng_err	25.000s	33.419us	468	500	93.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	15.717m	72.013ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.350m	6.392ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	24.000s	1.111ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	27.000s	1.722ms	180	200	90.00
		csrng_err	25.000s	33.419us	468	500	93.60
		csrng_sec_cm	6.000s	348.418us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	27.000s	1.722ms	180	200	90.00
		csrng_err	25.000s	33.419us	468	500	93.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	27.000s	1.722ms	180	200	90.00
		csrng_err	25.000s	33.419us	468	500	93.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	27.000s	1.722ms	180	200	90.00
		csrng_err	25.000s	33.419us	468	500	93.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	27.000s	1.722ms	180	200	90.00
		csrng_err	25.000s	33.419us	468	500	93.60
		csrng_sec_cm	6.000s	348.418us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	27.000s	1.722ms	180	200	90.00
		csrng_err	25.000s	33.419us	468	500	93.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	8.350m	23.673ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1576	1630	96.69

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.58	98.55	96.50	99.86	97.01	92.08	100.00	95.61	90.36

Failure Buckets

• UVM_FATAL (csrng_base_vseq.sv:184) virtual_sequencer [csrng_err_vseq] has 17 failures:
  • Test csrng_err has 17 failures.

    • 2.csrng_err.114124255383249124157901599361817922655350966341357977450711322606496576920891
      Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_err/latest/run.log

        UVM_FATAL @   8160343 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @   8160343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.csrng_err.56581172875322198150789110931262355241927290589436434626680729282136614199215
      Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/3.csrng_err/latest/run.log

        UVM_FATAL @   4304906 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @   4304906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 15 more failures.

• UVM_FATAL (csrng_base_vseq.sv:189) virtual_sequencer [csrng_err_vseq] has 15 failures:
  • Test csrng_err has 15 failures.

    • 17.csrng_err.85026542549441617153620252588198673946718185848096128787245724511840338212474
      Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/17.csrng_err/latest/run.log

        UVM_FATAL @   1823244 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @   1823244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 140.csrng_err.11177138426480654822423414316449180526648355119044596556123811022958712210910
      Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/140.csrng_err/latest/run.log

        UVM_FATAL @   2212654 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_err_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @   2212654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 13 more failures.

• UVM_FATAL (csrng_base_vseq.sv:184) virtual_sequencer [csrng_intr_vseq] has 11 failures:
  • Test csrng_intr has 11 failures.

    • 21.csrng_intr.105053786742465940696743312204982464899785382572761536297188404462818616897864
      Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/21.csrng_intr/latest/run.log

        UVM_FATAL @ 406583910 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @ 406583910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 31.csrng_intr.16891575267225866028964646629954631654605147230240912331618560683451573406590
      Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/31.csrng_intr/latest/run.log

        UVM_FATAL @ 409462929 ps: (csrng_base_vseq.sv:184) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @ 409462929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 9 more failures.

• UVM_FATAL (csrng_base_vseq.sv:189) virtual_sequencer [csrng_intr_vseq] has 9 failures:
  • Test csrng_intr has 9 failures.

    • 4.csrng_intr.13273055270684084322861802486306856431078689905641912909306281867402725217506
      Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/4.csrng_intr/latest/run.log

        UVM_FATAL @  45640869 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @  45640869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 15.csrng_intr.34736968536186606421340255792257245324155633382813634774250275973815785231682
      Line 146, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/15.csrng_intr/latest/run.log

        UVM_FATAL @ 130555055 ps: (csrng_base_vseq.sv:189) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.csrng_intr_vseq]
             ----| PATH NOT FOUND
        UVM_INFO @ 130555055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
  • Test csrng_stress_all has 2 failures.

    • 19.csrng_stress_all.92500669048487015037647897170810446126002417798006019885957715862676193681928
      Line 153, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/19.csrng_stress_all/latest/run.log

        UVM_ERROR @ 25651746161 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 25651746161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 25.csrng_stress_all.9580931859880109342465444965482821203007726200739543119381736033344277770797
      Line 156, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/25.csrng_stress_all/latest/run.log

        UVM_ERROR @  86265120 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @  86265120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---