DMA Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	286.763us	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	7.000s	553.186us	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	808.325us	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	18.929us	5	5	100.00
V1	csr_rw	dma_csr_rw	2.000s	23.516us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	13.000s	5.130ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	1.121ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	173.352us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	23.516us	20	20	100.00
		dma_csr_aliasing	7.000s	1.121ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.283m	16.003ms	5	5	100.00
V2	dma_memory_tl_error	dma_memory_stress	8.683m	187.738ms	3	3	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	6.483m	29.239ms	3	3	100.00
V2	dma_handshake_stress	dma_handshake_stress	6.483m	29.239ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	8.683m	187.738ms	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	7.133m	178.508ms	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	6.483m	29.239ms	3	3	100.00
V2	dma_abort	dma_abort	16.000s	1.038ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	7.450m	238.522ms	3	3	100.00
V2	alert_test	dma_alert_test	2.000s	75.550us	50	50	100.00
V2	intr_test	dma_intr_test	2.000s	37.469us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	3.000s	51.894us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	3.000s	51.894us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	18.929us	5	5	100.00
		dma_csr_rw	2.000s	23.516us	20	20	100.00
		dma_csr_aliasing	7.000s	1.121ms	5	5	100.00
		dma_same_csr_outstanding	3.000s	37.463us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	18.929us	5	5	100.00
		dma_csr_rw	2.000s	23.516us	20	20	100.00
		dma_csr_aliasing	7.000s	1.121ms	5	5	100.00
		dma_same_csr_outstanding	3.000s	37.463us	20	20	100.00
V2		TOTAL			164	164	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	25.000s	376.060us	5	5	100.00
		dma_generic_stress	7.133m	178.508ms	5	5	100.00
		dma_handshake_stress	6.483m	29.239ms	3	3	100.00
V2S	dma_config_lock	dma_config_lock	10.000s	636.195us	15	15	100.00
V2S	tl_intg_err	dma_tl_intg_err	4.000s	745.527us	20	20	100.00
		dma_sec_cm	2.000s	31.394us	5	5	100.00
V2S		TOTAL			45	45	100.00
	Unmapped tests	dma_short_transfer	2.550m	57.301ms	25	25	100.00
		dma_longer_transfer	6.617m	19.480ms	5	5	100.00
		dma_stress_all_with_rand_reset	9.000s	685.793us	0	1	0.00
		TOTAL			394	395	99.75

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.72	97.38	95.83	96.89	95.99	77.37	92.96	95.97	79.82

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.74067447531757891587760763755589015142022606438668419264969436564098557832456
      Line 113, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  685792584ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  685792584ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---