EDN Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.410s 19.044us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.060s 49.589us 5 5 100.00
V1 csr_rw edn_csr_rw 0.990s 49.076us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.680s 177.571us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.150s 37.147us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.480s 30.055us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.990s 49.076us 20 20 100.00
edn_csr_aliasing 1.150s 37.147us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 5.310s 676.964us 300 300 100.00
V2 csrng_commands edn_genbits 5.310s 676.964us 300 300 100.00
V2 genbits edn_genbits 5.310s 676.964us 300 300 100.00
V2 interrupts edn_intr 1.420s 41.553us 50 50 100.00
V2 alerts edn_alert 1.620s 91.649us 200 200 100.00
V2 errs edn_err 1.660s 21.544us 100 100 100.00
V2 disable edn_disable 1.330s 12.900us 50 50 100.00
edn_disable_auto_req_mode 1.680s 75.884us 50 50 100.00
V2 stress_all edn_stress_all 5.790s 407.087us 50 50 100.00
V2 intr_test edn_intr_test 1.060s 18.789us 50 50 100.00
V2 alert_test edn_alert_test 2.100s 133.457us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.480s 535.250us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.480s 535.250us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.060s 49.589us 5 5 100.00
edn_csr_rw 0.990s 49.076us 20 20 100.00
edn_csr_aliasing 1.150s 37.147us 5 5 100.00
edn_same_csr_outstanding 1.270s 33.013us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.060s 49.589us 5 5 100.00
edn_csr_rw 0.990s 49.076us 20 20 100.00
edn_csr_aliasing 1.150s 37.147us 5 5 100.00
edn_same_csr_outstanding 1.270s 33.013us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.930s 751.447us 5 5 100.00
edn_tl_intg_err 2.150s 118.053us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.270s 115.121us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.620s 91.649us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.930s 751.447us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.930s 751.447us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.930s 751.447us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.930s 751.447us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.620s 91.649us 200 200 100.00
edn_sec_cm 8.930s 751.447us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.620s 91.649us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.150s 118.053us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.831m 24.009ms 34 50 68.00
V3 TOTAL 34 50 68.00
TOTAL 1114 1130 98.58

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.38 98.87 94.23 97.02 90.70 96.33 97.56 92.94

Failure Buckets