HMAC Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	11.530s	1.167ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.070s	127.395us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.270s	32.041us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	13.830s	6.572ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	7.790s	153.590us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	14.135m	296.845ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.270s	32.041us	20	20	100.00
		hmac_csr_aliasing	7.790s	153.590us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.137m	56.973ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.561m	1.918ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	3.916m	22.294ms	30	30	100.00
		hmac_test_sha384_vectors	8.572m	18.043ms	75	75	100.00
		hmac_test_sha512_vectors	9.862m	126.592ms	75	75	100.00
		hmac_test_hmac256_vectors	15.020s	1.331ms	50	50	100.00
		hmac_test_hmac384_vectors	15.920s	1.547ms	60	60	100.00
		hmac_test_hmac512_vectors	18.310s	363.718us	75	75	100.00
V2	burst_wr	hmac_burst_wr	46.600s	10.931ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	22.946m	31.027ms	10	10	100.00
V2	error	hmac_error	1.250m	26.447ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.604m	11.330ms	10	10	100.00
V2	save_and_restore	hmac_smoke	11.530s	1.167ms	10	10	100.00
		hmac_long_msg	1.137m	56.973ms	10	10	100.00
		hmac_back_pressure	1.561m	1.918ms	25	25	100.00
		hmac_datapath_stress	22.946m	31.027ms	10	10	100.00
		hmac_burst_wr	46.600s	10.931ms	50	50	100.00
		hmac_stress_all	42.854m	358.489ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	11.530s	1.167ms	10	10	100.00
		hmac_long_msg	1.137m	56.973ms	10	10	100.00
		hmac_back_pressure	1.561m	1.918ms	25	25	100.00
		hmac_datapath_stress	22.946m	31.027ms	10	10	100.00
		hmac_wipe_secret	1.604m	11.330ms	10	10	100.00
		hmac_test_sha256_vectors	3.916m	22.294ms	30	30	100.00
		hmac_test_sha384_vectors	8.572m	18.043ms	75	75	100.00
		hmac_test_sha512_vectors	9.862m	126.592ms	75	75	100.00
		hmac_test_hmac256_vectors	15.020s	1.331ms	50	50	100.00
		hmac_test_hmac384_vectors	15.920s	1.547ms	60	60	100.00
		hmac_test_hmac512_vectors	18.310s	363.718us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	11.530s	1.167ms	10	10	100.00
		hmac_long_msg	1.137m	56.973ms	10	10	100.00
		hmac_back_pressure	1.561m	1.918ms	25	25	100.00
		hmac_datapath_stress	22.946m	31.027ms	10	10	100.00
		hmac_burst_wr	46.600s	10.931ms	50	50	100.00
		hmac_error	1.250m	26.447ms	10	10	100.00
		hmac_wipe_secret	1.604m	11.330ms	10	10	100.00
		hmac_test_sha256_vectors	3.916m	22.294ms	30	30	100.00
		hmac_test_sha384_vectors	8.572m	18.043ms	75	75	100.00
		hmac_test_sha512_vectors	9.862m	126.592ms	75	75	100.00
		hmac_test_hmac256_vectors	15.020s	1.331ms	50	50	100.00
		hmac_test_hmac384_vectors	15.920s	1.547ms	60	60	100.00
		hmac_test_hmac512_vectors	18.310s	363.718us	75	75	100.00
		hmac_stress_all	42.854m	358.489ms	50	50	100.00
V2	stress_all	hmac_stress_all	42.854m	358.489ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.930s	13.515us	50	50	100.00
V2	intr_test	hmac_intr_test	0.970s	17.166us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.290s	357.420us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.290s	357.420us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.070s	127.395us	5	5	100.00
		hmac_csr_rw	1.270s	32.041us	20	20	100.00
		hmac_csr_aliasing	7.790s	153.590us	5	5	100.00
		hmac_same_csr_outstanding	2.670s	123.433us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.070s	127.395us	5	5	100.00
		hmac_csr_rw	1.270s	32.041us	20	20	100.00
		hmac_csr_aliasing	7.790s	153.590us	5	5	100.00
		hmac_same_csr_outstanding	2.670s	123.433us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.310s	1.586ms	5	5	100.00
		hmac_tl_intg_err	4.970s	622.510us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.970s	622.510us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	11.530s	1.167ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	5.940s	121.049us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	9.418m	7.639ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	0.940s	13.408us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.16	99.95	96.74	100.00	100.00	99.83	97.61	100.00