I2C Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.456m	1.928ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	31.170s	2.768ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.090s	29.112us	5	5	100.00
V1	csr_rw	i2c_csr_rw	1.080s	38.823us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.570s	420.408us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.240s	106.255us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.490s	31.138us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.080s	38.823us	20	20	100.00
		i2c_csr_aliasing	2.240s	106.255us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	13.760s	1.414ms	2	50	4.00
V2	host_stress_all	i2c_host_stress_all	52.631m	51.570ms	8	50	16.00
V2	host_maxperf	i2c_host_perf	25.097m	74.446ms	50	50	100.00
V2	host_override	i2c_host_override	1.050s	25.305us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.996m	18.286ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.659m	2.348ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.670s	149.674us	50	50	100.00
		i2c_host_fifo_fmt_empty	25.350s	533.135us	50	50	100.00
		i2c_host_fifo_reset_rx	12.110s	236.900us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.428m	3.418ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	36.700s	1.617ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	4.830s	131.902us	14	50	28.00
V2	target_glitch	i2c_target_glitch	3.370s	2.203ms	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	34.674m	84.564ms	48	50	96.00
V2	target_maxperf	i2c_target_perf	8.540s	9.511ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.259m	3.870ms	50	50	100.00
		i2c_target_intr_smoke	9.540s	3.100ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.400s	311.917us	50	50	100.00
		i2c_target_fifo_reset_tx	2.700s	499.971us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	24.311m	74.012ms	50	50	100.00
		i2c_target_stress_rd	1.259m	3.870ms	50	50	100.00
		i2c_target_intr_stress_wr	6.367m	25.995ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	9.850s	5.942ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	2.920m	4.339ms	44	50	88.00
V2	bad_address	i2c_target_bad_addr	8.740s	5.078ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	35.910s	10.014ms	20	50	40.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	4.730s	2.523ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	2.030s	605.316us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	25.097m	74.446ms	50	50	100.00
		i2c_host_perf_precise	16.500m	24.205ms	49	50	98.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	36.700s	1.617ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	13.770s	946.175us	46	50	92.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	4.490s	1.214ms	50	50	100.00
		i2c_target_nack_acqfull_addr	3.990s	1.059ms	50	50	100.00
		i2c_target_nack_txstretch	2.310s	228.809us	30	50	60.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	20.210s	1.340ms	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.550s	1.924ms	50	50	100.00
V2	alert_test	i2c_alert_test	1.010s	16.745us	50	50	100.00
V2	intr_test	i2c_intr_test	1.060s	62.879us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.550s	196.535us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.550s	196.535us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.090s	29.112us	5	5	100.00
		i2c_csr_rw	1.080s	38.823us	20	20	100.00
		i2c_csr_aliasing	2.240s	106.255us	5	5	100.00
		i2c_same_csr_outstanding	1.550s	94.818us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.090s	29.112us	5	5	100.00
		i2c_csr_rw	1.080s	38.823us	20	20	100.00
		i2c_csr_aliasing	2.240s	106.255us	5	5	100.00
		i2c_same_csr_outstanding	1.550s	94.818us	20	20	100.00
V2		TOTAL			1601	1792	89.34
V2S	tl_intg_err	i2c_tl_intg_err	2.560s	146.001us	20	20	100.00
		i2c_sec_cm	1.450s	72.444us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.560s	146.001us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	45.790s	1.165ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.050s	1.566ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	33.970s	1.688ms	1	10	10.00
V3		TOTAL			1	70	1.43
		TOTAL			1782	2042	87.27

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
84.01	97.25	89.25	74.17	47.62	93.83	96.41	89.53

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 90 failures:

Test i2c_host_error_intr has 47 failures.

0.i2c_host_error_intr.93676124486777883935361729161063936885098488199510743355310197438925588870378
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  23426836 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  23426836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_error_intr.46454487533715230179243964089880207411199286965537877081918120259843199670142
Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 1413896046 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 1413896046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 45 more failures.

Test i2c_host_stress_all has 29 failures.

1.i2c_host_stress_all.50026644395618199914455624393524546319517715614857874320181152418368545581413
Line 144, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 38948531231 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 38948531231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_host_stress_all.107819509936660108872642997986831225716868079493996688536776876818047213871418
Line 136, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 35235893034 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 35235893034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 27 more failures.

Test i2c_host_mode_toggle has 11 failures.

5.i2c_host_mode_toggle.32792898733831404766422465454613419305814263632503576798472870097065809575986
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @   5653298 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @   5653298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.i2c_host_mode_toggle.23748119210368438152767234049440354417184703382889720675644305922682509077354
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  17186000 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  17186000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test i2c_target_stress_all_with_rand_reset has 3 failures.

6.i2c_target_stress_all_with_rand_reset.114574915927153007300533333472596703323014768252509255859596189885973326719631
Line 93, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 131370742 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 131370742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.i2c_target_stress_all_with_rand_reset.33091894011892028190167734120919678242468332856725298603324114742318946016644
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 166542902 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 166542902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 30 failures:
- Test i2c_target_hrst has 30 failures.
  - 1.i2c_target_hrst.9529751654849184078040896981354190759353157671224696555403686183083598633422
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10093684380 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10093684380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_hrst.11405972991201257521189390881627104509557383774884010725887780746990601910647
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10234624574 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10234624574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 28 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 29 failures:
- Test i2c_target_unexp_stop has 29 failures.
  - 0.i2c_target_unexp_stop.23833873306738297603989796615328688916556631057368741406136531864094883034525
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 563615296 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 162 [0xa2])
  UVM_INFO @ 563615296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_unexp_stop.19679196854472813920279039563865658021853818308989718383822517752398920757537
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 710996128 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 96 [0x60])
  UVM_INFO @ 710996128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 27 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 20 failures:
- Test i2c_target_unexp_stop has 20 failures.
  - 1.i2c_target_unexp_stop.112274378365984608392753595832868007531665945025592594020095845692725617281416
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 513510409 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 513510409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_unexp_stop.88425952018118520825194256612706399208256674110921953337114196085493709806103
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 132398882 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 132398882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 18 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 20 failures:
- Test i2c_target_nack_txstretch has 20 failures.
  - 5.i2c_target_nack_txstretch.7404513363008698952656713483774415221838365718910900525176285225910107174421
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 711959014 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 711959014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.i2c_target_nack_txstretch.84555276594132312260477757789914510632325154457751183523574878797081372078097
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 228808980 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 228808980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 18 more failures.

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 17 failures:

Test i2c_host_mode_toggle has 11 failures.

1.i2c_host_mode_toggle.70720173760725247733815035734207187261833040633563234543355127353550350655490
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 631696413 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @59958

3.i2c_host_mode_toggle.82986408416690073827525013124747848593432782158582482089646685899271625693736
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 324283893 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @48784

... and 9 more failures.

Test i2c_host_stress_all has 6 failures.

3.i2c_host_stress_all.38814967851601418873987534922738067262997838006187244992889225550134349093681
Line 233, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 28357550594 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4813189

9.i2c_host_stress_all.96082757295332946404819729692713026258118653819960210892515628942342232055154
Line 154, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 70161718265 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @24162259

... and 4 more failures.

UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.49114842252328066741064677035231100251149067128914650831299686108637946588773
Line 95, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9096538430 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9096538430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.23398815879926962357329956898086637512927850172376473345398212943154436391653
Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1215291699 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1215291699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 4 failures.

1.i2c_target_stress_all_with_rand_reset.114451029443591231456496134611150052070590303990208579936335614501044408347178
Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 794614141 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 794614141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.42010925741824232126713396366810646258742756585054476281939537697869709262966
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1046797390 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1046797390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 8 failures:

Test i2c_host_mode_toggle has 7 failures.

6.i2c_host_mode_toggle.68514682804523887314474815429530182758488318692205843295806297562613651723473
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 218303567 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

12.i2c_host_mode_toggle.77504722638771079234345383670788685933772149014810238974386350055620943735805
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/12.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  47814140 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 5 more failures.

Test i2c_host_perf_precise has 1 failures.

27.i2c_host_perf_precise.71678914709788318342373390564248787838232019371789539720495057603591925294395
Line 79, in log /nightly/current_run/scratch/master/i2c-sim-vcs/27.i2c_host_perf_precise/latest/run.log

  UVM_ERROR @ 439458776 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 6 failures:
- Test i2c_target_stretch has 6 failures.
  - 8.i2c_target_stretch.42186281724658411884620103932638116733670284138891872869793805835483534683556
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10012450917 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10012450917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 30.i2c_target_stretch.89282086074331801659911469641838003387784179225816404117845615024647024915525
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/30.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10011809498 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10011809498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
Job timed out after * minutes has 5 failures:
- Test i2c_host_stress_all has 5 failures.
  - 5.i2c_host_stress_all.32066891079805026859121197821806139109835466125192569441896359257469443701805
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 8.i2c_host_stress_all.106170921325049419977338066125693005295938958550682133120944282035492034477016
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 3 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
- Test i2c_target_tx_stretch_ctrl has 4 failures.
  - 9.i2c_target_tx_stretch_ctrl.26572785916541614355043274487845153330225257501196502748264582057589156932557
    Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 18.i2c_target_tx_stretch_ctrl.1090709544894785094691803941246904643620006467574519703931865140902765360252
    Line 127, in log /nightly/current_run/scratch/master/i2c-sim-vcs/18.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
- Test i2c_host_mode_toggle has 4 failures.
  - 19.i2c_host_mode_toggle.76078517611036030566986528102258625626530104532067928168924735988958965644351
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/19.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  79810350 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xfbe77014, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  79810350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 23.i2c_host_mode_toggle.108244079483510686877895328565790660780731038162401666310594067977482187634060
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/23.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  24827414 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x93aed694, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  24827414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
Error-[NOA] Null object access has 3 failures:
- Test i2c_host_mode_toggle has 3 failures.
  - 8.i2c_host_mode_toggle.63579283174296868362180634376992702336251555209222691254692711573383302652549
    Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
  - 31.i2c_host_mode_toggle.91947180736237685656197813676503235077520550451500912727802812288814951526173
    Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/31.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
  - ... and 1 more failures.

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.2004521970739696124180970061163748988025462780799267076227741940476024886987
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 1059836910 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 1059836910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.97668057307097580211095003743660129381262949223749195483644603605402819532428
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 2202530945 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 2202530945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 2.i2c_target_stress_all_with_rand_reset.24043922551444397910325812999545903630531061024967901195741383867650074971247
    Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 595417054 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 595417054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.i2c_target_stress_all_with_rand_reset.91173611057401453260592420584058387303895705881305449824247157716853906768269
    Line 94, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1688237067 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1688237067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 2 failures.

18.i2c_host_stress_all.81084758015594380281651986825674526746456895592692594040064155447748673287097
Line 132, in log /nightly/current_run/scratch/master/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 29020036540 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @16485231

40.i2c_host_stress_all.86305691863970170937132961412107332035091339051930311618569056203883092832514
Line 164, in log /nightly/current_run/scratch/master/i2c-sim-vcs/40.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 28152211892 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @5834775

UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
- Test i2c_target_stress_all has 2 failures.
  - 26.i2c_target_stress_all.72641380780745169669226404021430123358914119802368253827918290847102367154207
    Line 110, in log /nightly/current_run/scratch/master/i2c-sim-vcs/26.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 77551400757 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 77551400757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 43.i2c_target_stress_all.14114637628767348174412406850518157125999300377188030845261289295313117120062
    Line 102, in log /nightly/current_run/scratch/master/i2c-sim-vcs/43.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 63029872056 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 63029872056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
- Test i2c_host_error_intr has 1 failures.
  - 18.i2c_host_error_intr.62672868413771755076615097505298438485080429878304678771565671023681195568263
    Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/18.i2c_host_error_intr/latest/run.log
```
  UVM_ERROR @  74507745 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
```
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 35.i2c_target_unexp_stop.49750544560292433729356847203551235414090259291947854172488310937760022370419
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/35.i2c_target_unexp_stop/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 327429699 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 327429699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```