KEYMGR Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	20.880s	1.056ms	50	50	100.00
V1	random	keymgr_random	49.740s	5.390ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.560s	58.301us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.730s	122.254us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	13.210s	4.921ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.260s	1.655ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.160s	132.149us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.730s	122.254us	20	20	100.00
		keymgr_csr_aliasing	8.260s	1.655ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.529m	9.698ms	50	50	100.00
V2	sideload	keymgr_sideload	17.420s	1.143ms	50	50	100.00
		keymgr_sideload_kmac	55.070s	9.716ms	50	50	100.00
		keymgr_sideload_aes	36.490s	1.503ms	50	50	100.00
		keymgr_sideload_otbn	21.540s	2.930ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	22.960s	2.033ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	30.500s	5.526ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	14.610s	862.564us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.077m	2.633ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	41.130s	5.837ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	17.030s	2.356ms	49	50	98.00
V2	stress_all	keymgr_stress_all	5.569m	14.902ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.350s	26.823us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.380s	18.622us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.950s	562.982us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.950s	562.982us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.560s	58.301us	5	5	100.00
		keymgr_csr_rw	1.730s	122.254us	20	20	100.00
		keymgr_csr_aliasing	8.260s	1.655ms	5	5	100.00
		keymgr_same_csr_outstanding	3.750s	250.177us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.560s	58.301us	5	5	100.00
		keymgr_csr_rw	1.730s	122.254us	20	20	100.00
		keymgr_csr_aliasing	8.260s	1.655ms	5	5	100.00
		keymgr_same_csr_outstanding	3.750s	250.177us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	sec_cm_additional_check	keymgr_sec_cm	25.160s	1.674ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	25.160s	1.674ms	5	5	100.00
		keymgr_tl_intg_err	7.680s	988.790us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.600s	404.163us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.600s	404.163us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.600s	404.163us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.600s	404.163us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	10.640s	233.144us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	25.160s	1.674ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	25.160s	1.674ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.680s	988.790us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.600s	404.163us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.529m	9.698ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	49.740s	5.390ms	50	50	100.00
		keymgr_csr_rw	1.730s	122.254us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	49.740s	5.390ms	50	50	100.00
		keymgr_csr_rw	1.730s	122.254us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	49.740s	5.390ms	50	50	100.00
		keymgr_csr_rw	1.730s	122.254us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	30.500s	5.526ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	41.130s	5.837ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	41.130s	5.837ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	49.740s	5.390ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	11.430s	567.846us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	25.160s	1.674ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	25.160s	1.674ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	25.160s	1.674ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	14.260s	3.160ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	30.500s	5.526ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	25.160s	1.674ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	25.160s	1.674ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	25.160s	1.674ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	14.260s	3.160ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	14.260s	3.160ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	25.160s	1.674ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	14.260s	3.160ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	25.160s	1.674ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	14.260s	3.160ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	24.340s	15.528ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1085	1110	97.75

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.32	99.09	97.99	98.67	97.67	98.92	97.71	91.18

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test keymgr_stress_all_with_rand_reset has 19 failures.
  - 7.keymgr_stress_all_with_rand_reset.72963268200256204921307357969164339219154750548697107192241838746715268841607
    Line 168, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 107725737 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 107725737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 11.keymgr_stress_all_with_rand_reset.112180972951336198374652721995255649894932742826020007926449786114333616871613
    Line 562, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 305990478 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 305990478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.
UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 6.keymgr_stress_all_with_rand_reset.57158006023067670293307021369208523446634482967131627269756064042849950985647
    Line 445, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 729517625 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (4 [0x4] vs 6 [0x6])
  UVM_INFO @ 729517625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1142) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 10.keymgr_stress_all_with_rand_reset.50723839368198804959711709404661553305381485179685597537856183871203844040095
    Line 509, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 605451441 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 605451441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [*] vs * [*]) has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 11.keymgr_sync_async_fault_cross.46969565327387723764072653050477767466838059245921995998738066414642036996886
    Line 167, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  40131887 ps: (keymgr_sync_async_fault_cross_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] ||                 act_fault_status[keymgr_pkg::FaultKmacOut] == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  40131887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Sealing Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

21.keymgr_stress_all.27774286700204361575537073266788360648961128068264414283580587668162875924692
Line 764, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/21.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 297719501 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (12112857998607375074959382861948344651694127585144835789278816977577069589782711630952746093500208949588872301264553908777464604446663269312798999019599269 [0xe7466aa556a3d7d9b97ff895288f78f350121d586f9365a2b7a3971d085b24ea287e244aec2ce7915eae6d17bf313b8e452318694c74286b3fddb622991d35a5] vs 12112857998607375074959382861948344651694127585144835789278816977577069589782711630952746093500208949588872301264553908777464604446663269312798999019599269 [0xe7466aa556a3d7d9b97ff895288f78f350121d586f9365a2b7a3971d085b24ea287e244aec2ce7915eae6d17bf313b8e452318694c74286b3fddb622991d35a5]) AES key at state StCreatorRootKey for Sealing Aes
  UVM_INFO @ 297719501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 26.keymgr_stress_all.31227882656218860235727810052728536220675573713016092187629826808596246599978
    Line 667, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/26.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 270327594 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (4281478660 [0xff322e04] vs 4281478660 [0xff322e04]) reg name: keymgr_reg_block.sw_share0_output_5
  UVM_INFO @ 270327594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 32.keymgr_stress_all_with_rand_reset.8311828370448242597054695308249775633472215339325375565116116902740985333616
    Line 2723, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 484500197 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 484500197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```