c5877ed| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | keymgr_dpe_smoke | 7.148m | 82.309ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | keymgr_dpe_csr_hw_reset | 1.510s | 105.484us | 4 | 5 | 80.00 |
| V1 | csr_rw | keymgr_dpe_csr_rw | 1.720s | 22.056us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | keymgr_dpe_csr_bit_bash | 12.690s | 1.192ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | keymgr_dpe_csr_aliasing | 6.650s | 919.611us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | keymgr_dpe_csr_mem_rw_with_rand_reset | 2.800s | 33.108us | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_dpe_csr_rw | 1.720s | 22.056us | 20 | 20 | 100.00 |
| keymgr_dpe_csr_aliasing | 6.650s | 919.611us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 103 | 105 | 98.10 | |||
| V2 | intr_test | keymgr_dpe_intr_test | 1.260s | 12.666us | 50 | 50 | 100.00 |
| V2 | alert_test | keymgr_dpe_alert_test | 1.300s | 69.341us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | keymgr_dpe_tl_errors | 3.420s | 274.300us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | keymgr_dpe_tl_errors | 3.420s | 274.300us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | keymgr_dpe_csr_hw_reset | 1.510s | 105.484us | 4 | 5 | 80.00 |
| keymgr_dpe_csr_rw | 1.720s | 22.056us | 20 | 20 | 100.00 | ||
| keymgr_dpe_csr_aliasing | 6.650s | 919.611us | 5 | 5 | 100.00 | ||
| keymgr_dpe_same_csr_outstanding | 3.260s | 195.444us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | keymgr_dpe_csr_hw_reset | 1.510s | 105.484us | 4 | 5 | 80.00 |
| keymgr_dpe_csr_rw | 1.720s | 22.056us | 20 | 20 | 100.00 | ||
| keymgr_dpe_csr_aliasing | 6.650s | 919.611us | 5 | 5 | 100.00 | ||
| keymgr_dpe_same_csr_outstanding | 3.260s | 195.444us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 140 | 140 | 100.00 | |||
| V2S | tl_intg_err | keymgr_dpe_sec_cm | 9.680s | 367.565us | 5 | 5 | 100.00 |
| keymgr_dpe_tl_intg_err | 6.950s | 944.426us | 20 | 20 | 100.00 | ||
| V2S | shadow_reg_update_error | keymgr_dpe_shadow_reg_errors | 2.810s | 948.661us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | keymgr_dpe_shadow_reg_errors | 2.810s | 948.661us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | keymgr_dpe_shadow_reg_errors | 2.810s | 948.661us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | keymgr_dpe_shadow_reg_errors | 2.810s | 948.661us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | keymgr_dpe_shadow_reg_errors_with_csr_rw | 7.420s | 288.023us | 20 | 20 | 100.00 |
| V2S | prim_count_check | keymgr_dpe_sec_cm | 9.680s | 367.565us | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | keymgr_dpe_sec_cm | 9.680s | 367.565us | 5 | 5 | 100.00 |
| V2S | TOTAL | 65 | 65 | 100.00 | |||
| TOTAL | 308 | 310 | 99.35 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 76.59 | 97.62 | 90.26 | 63.15 | 75.68 | 94.61 | 97.62 | 17.22 |
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: keymgr_dpe_reg_block.debug reset value: * has 1 failures:
2.keymgr_dpe_csr_hw_reset.333323263261093049690885962793890584837389156845115765706632175591708157501
Line 82, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/2.keymgr_dpe_csr_hw_reset/latest/run.log
UVM_ERROR @ 8987709 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (256 [0x100] vs 0 [0x0]) Regname: keymgr_dpe_reg_block.debug reset value: 0x0
UVM_INFO @ 8987709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: keymgr_dpe_reg_block.max_key_ver_regwen reset value: * has 1 failures:
11.keymgr_dpe_csr_mem_rw_with_rand_reset.62097394377884549710168962282969529399742867137282610768059595719922901364414
Line 86, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/11.keymgr_dpe_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 52173226 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: keymgr_dpe_reg_block.max_key_ver_regwen reset value: 0x1
UVM_INFO @ 52173226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---