KEYMGR_DPE Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_dpe_smoke 7.148m 82.309ms 50 50 100.00
V1 csr_hw_reset keymgr_dpe_csr_hw_reset 1.510s 105.484us 4 5 80.00
V1 csr_rw keymgr_dpe_csr_rw 1.720s 22.056us 20 20 100.00
V1 csr_bit_bash keymgr_dpe_csr_bit_bash 12.690s 1.192ms 5 5 100.00
V1 csr_aliasing keymgr_dpe_csr_aliasing 6.650s 919.611us 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_dpe_csr_mem_rw_with_rand_reset 2.800s 33.108us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_dpe_csr_rw 1.720s 22.056us 20 20 100.00
keymgr_dpe_csr_aliasing 6.650s 919.611us 5 5 100.00
V1 TOTAL 103 105 98.10
V2 intr_test keymgr_dpe_intr_test 1.260s 12.666us 50 50 100.00
V2 alert_test keymgr_dpe_alert_test 1.300s 69.341us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_dpe_tl_errors 3.420s 274.300us 20 20 100.00
V2 tl_d_illegal_access keymgr_dpe_tl_errors 3.420s 274.300us 20 20 100.00
V2 tl_d_outstanding_access keymgr_dpe_csr_hw_reset 1.510s 105.484us 4 5 80.00
keymgr_dpe_csr_rw 1.720s 22.056us 20 20 100.00
keymgr_dpe_csr_aliasing 6.650s 919.611us 5 5 100.00
keymgr_dpe_same_csr_outstanding 3.260s 195.444us 20 20 100.00
V2 tl_d_partial_access keymgr_dpe_csr_hw_reset 1.510s 105.484us 4 5 80.00
keymgr_dpe_csr_rw 1.720s 22.056us 20 20 100.00
keymgr_dpe_csr_aliasing 6.650s 919.611us 5 5 100.00
keymgr_dpe_same_csr_outstanding 3.260s 195.444us 20 20 100.00
V2 TOTAL 140 140 100.00
V2S tl_intg_err keymgr_dpe_sec_cm 9.680s 367.565us 5 5 100.00
keymgr_dpe_tl_intg_err 6.950s 944.426us 20 20 100.00
V2S shadow_reg_update_error keymgr_dpe_shadow_reg_errors 2.810s 948.661us 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_dpe_shadow_reg_errors 2.810s 948.661us 20 20 100.00
V2S shadow_reg_storage_error keymgr_dpe_shadow_reg_errors 2.810s 948.661us 20 20 100.00
V2S shadowed_reset_glitch keymgr_dpe_shadow_reg_errors 2.810s 948.661us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_dpe_shadow_reg_errors_with_csr_rw 7.420s 288.023us 20 20 100.00
V2S prim_count_check keymgr_dpe_sec_cm 9.680s 367.565us 5 5 100.00
V2S prim_fsm_check keymgr_dpe_sec_cm 9.680s 367.565us 5 5 100.00
V2S TOTAL 65 65 100.00
TOTAL 308 310 99.35

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
76.59 97.62 90.26 63.15 75.68 94.61 97.62 17.22

Failure Buckets