KMAC/MASKED Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.594m	5.002ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.320s	95.216us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.490s	29.007us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.250s	7.966ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.230s	637.397us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.290s	139.331us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.490s	29.007us	20	20	100.00
		kmac_csr_aliasing	6.230s	637.397us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.030s	15.024us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.720s	68.292us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	1.058h	750.460ms	50	50	100.00
V2	burst_write	kmac_burst_write	22.243m	34.393ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	26.403m	34.304ms	5	5	100.00
		kmac_test_vectors_sha3_256	34.628m	186.233ms	5	5	100.00
		kmac_test_vectors_sha3_384	24.851m	47.490ms	5	5	100.00
		kmac_test_vectors_sha3_512	20.014m	83.228ms	5	5	100.00
		kmac_test_vectors_shake_128	43.182m	1.207s	5	5	100.00
		kmac_test_vectors_shake_256	38.537m	180.758ms	5	5	100.00
		kmac_test_vectors_kmac	3.400s	278.464us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.530s	116.105us	5	5	100.00
V2	sideload	kmac_sideload	8.260m	20.462ms	50	50	100.00
V2	app	kmac_app	6.846m	132.025ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.937m	25.190ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.852m	70.373ms	50	50	100.00
V2	error	kmac_error	7.730m	35.839ms	50	50	100.00
V2	key_error	kmac_key_error	18.770s	7.706ms	49	50	98.00
V2	sideload_invalid	kmac_sideload_invalid	9.310s	1.244ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.610s	1.795ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	44.810s	9.197ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.265m	7.812ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	29.060s	13.364ms	50	50	100.00
V2	stress_all	kmac_stress_all	39.093m	115.318ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.120s	17.132us	50	50	100.00
V2	alert_test	kmac_alert_test	1.510s	164.176us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.810s	2.463ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.810s	2.463ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.320s	95.216us	5	5	100.00
		kmac_csr_rw	1.490s	29.007us	20	20	100.00
		kmac_csr_aliasing	6.230s	637.397us	5	5	100.00
		kmac_same_csr_outstanding	2.960s	430.948us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.320s	95.216us	5	5	100.00
		kmac_csr_rw	1.490s	29.007us	20	20	100.00
		kmac_csr_aliasing	6.230s	637.397us	5	5	100.00
		kmac_same_csr_outstanding	2.960s	430.948us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.080s	1.104ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.080s	1.104ms	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.080s	1.104ms	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.080s	1.104ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.470s	227.953us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.583m	17.297ms	5	5	100.00
		kmac_tl_intg_err	4.410s	468.918us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.410s	468.918us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	29.060s	13.364ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.594m	5.002ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.260m	20.462ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.080s	1.104ms	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.583m	17.297ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.583m	17.297ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.583m	17.297ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.594m	5.002ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	29.060s	13.364ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.583m	17.297ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.725m	72.039ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.594m	5.002ms	49	50	98.00
V2S		TOTAL			74	75	98.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.391m	5.066ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			935	940	99.47

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.93	99.20	94.45	99.89	78.17	97.08	97.83	97.86

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:

  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 0.kmac_stress_all_with_rand_reset.53228345230338384995253938689929569788436329296405082260780250364146761111322
      Line 555, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5065570457 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 5065570457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 8.kmac_stress_all_with_rand_reset.38742216203275927789486959763589348714081454725296180207620539443574734526963
      Line 328, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3267735374 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 3267735374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 4.kmac_shadow_reg_errors_with_csr_rw.71675215260387583658599965109460322401984986884506997626838438422304704224335
      Line 364, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @ 930154903 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1364514816 [0x5154d800] vs 0 [0x0]) Regname: kmac_reg_block.prefix_3.prefix_0 reset value: 0x0
        UVM_INFO @ 930154903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:

  • Test kmac_key_error has 1 failures.

    • 16.kmac_key_error.22145472983916548910973326268503224174877995531797820769565347591828187231456
      Line 78, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_key_error/latest/run.log

        UVM_ERROR @ 176289076 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
        UVM_INFO @ 176289076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_smoke has 1 failures.

    • 31.kmac_smoke.82490746758751085210288496048148088008427950567104615856144948444782964713769
      Line 74, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/31.kmac_smoke/latest/run.log

        UVM_ERROR @ 186996074 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @ 186996074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---