MBX Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	54.000s	4.148ms	2	2	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	2.000s	31.803us	5	5	100.00
V1	csr_rw	mbx_csr_rw	2.000s	40.104us	20	20	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	4.000s	297.488us	5	5	100.00
V1	csr_aliasing	mbx_csr_aliasing	2.000s	81.423us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	3.000s	295.802us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	2.000s	40.104us	20	20	100.00
		mbx_csr_aliasing	2.000s	81.423us	5	5	100.00
V1		TOTAL			57	57	100.00
V2	mbx_stress	mbx_stress	1.050m	11.726ms	1	2	50.00
V2	mbx_max_activity	mbx_stress_zero_delays	2.167m	82.911ms	1	2	50.00
V2	mbx_imbx_oob	mbx_imbx_oob	38.000s	13.015ms	1	2	50.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	17.000s	558.412us	5	5	100.00
V2	alert_test	mbx_alert_test	2.000s	13.703us	50	50	100.00
V2	intr_test	mbx_intr_test	6.000s	30.302us	50	50	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	4.000s	235.208us	20	20	100.00
V2	tl_d_illegal_access	mbx_tl_errors	4.000s	235.208us	20	20	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	2.000s	31.803us	5	5	100.00
		mbx_csr_rw	2.000s	40.104us	20	20	100.00
		mbx_csr_aliasing	2.000s	81.423us	5	5	100.00
		mbx_same_csr_outstanding	2.000s	33.328us	20	20	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	2.000s	31.803us	5	5	100.00
		mbx_csr_rw	2.000s	40.104us	20	20	100.00
		mbx_csr_aliasing	2.000s	81.423us	5	5	100.00
		mbx_same_csr_outstanding	2.000s	33.328us	20	20	100.00
V2		TOTAL			148	151	98.01
V2S	tl_intg_err	mbx_tl_intg_err	3.000s	261.452us	20	20	100.00
		mbx_sec_cm	2.000s	20.567us	5	5	100.00
V2S		TOTAL			25	25	100.00
		TOTAL			230	233	98.71

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.65	96.88	92.43	96.86	91.52	79.67	--	97.01	86.33

Failure Buckets

• UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched has 2 failures:

  • Test mbx_stress has 1 failures.

    • 0.mbx_stress.102169461938455901991760607225167411120152404972126495435706015244209578797295
      Line 92, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log

        UVM_ERROR @  90709408 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (1591683103 [0x5edf281f] vs 0 [0x0]) RDATA read data mismatched
        UVM_INFO @  90709408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test mbx_stress_zero_delays has 1 failures.

    • 0.mbx_stress_zero_delays.4182628465658431076319990353556565020790182598569043204135537780528414189643
      Line 129, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log

        UVM_ERROR @  97286232 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (2148177016 [0x800a9478] vs 0 [0x0]) RDATA read data mismatched
        UVM_INFO @  97286232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 1 failures:

  • Test mbx_imbx_oob has 1 failures.

    • 0.mbx_imbx_oob.104952822255721701682335402382097112618505564858550142308282955002923994105510
      Line 93, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest/run.log

        UVM_ERROR @ 204922239 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 204922239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---