OTBN Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 14.000s 139.154us 0 1 0.00
V1 single_binary otbn_single 1.883m 458.103us 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 4.000s 48.693us 5 5 100.00
V1 csr_rw otbn_csr_rw 7.000s 27.130us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 8.000s 359.537us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 5.000s 16.370us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 9.000s 41.794us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 7.000s 27.130us 20 20 100.00
otbn_csr_aliasing 5.000s 16.370us 5 5 100.00
V1 mem_walk otbn_mem_walk 34.000s 1.389ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 19.000s 1.711ms 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 50.000s 170.119us 0 10 0.00
V2 multi_error otbn_multi_err 58.000s 180.112us 0 1 0.00
V2 back_to_back otbn_multi 7.867m 3.208ms 0 10 0.00
V2 stress_all otbn_stress_all 1.767m 270.393us 0 10 0.00
V2 lc_escalation otbn_escalate 21.000s 128.387us 18 60 30.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 12.000s 266.413us 1 5 20.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 58.000s 200.961us 0 10 0.00
V2 alert_test otbn_alert_test 7.000s 24.920us 50 50 100.00
V2 intr_test otbn_intr_test 7.000s 26.805us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 9.000s 130.153us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 9.000s 130.153us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 4.000s 48.693us 5 5 100.00
otbn_csr_rw 7.000s 27.130us 20 20 100.00
otbn_csr_aliasing 5.000s 16.370us 5 5 100.00
otbn_same_csr_outstanding 5.000s 25.398us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 4.000s 48.693us 5 5 100.00
otbn_csr_rw 7.000s 27.130us 20 20 100.00
otbn_csr_aliasing 5.000s 16.370us 5 5 100.00
otbn_same_csr_outstanding 5.000s 25.398us 20 20 100.00
V2 TOTAL 159 246 64.63
V2S mem_integrity otbn_imem_err 10.000s 18.773us 2 10 20.00
otbn_dmem_err 14.000s 33.250us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 15.000s 130.114us 0 5 0.00
otbn_controller_ispr_rdata_err 12.000s 112.790us 0 5 0.00
otbn_mac_bignum_acc_err 16.000s 94.465us 0 5 0.00
otbn_urnd_err 5.000s 19.316us 2 2 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 9.000s 89.282us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 13.000s 41.385us 1 2 50.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 10.000s 44.465us 10 10 100.00
V2S tl_intg_err otbn_sec_cm 4.150m 2.143ms 3 5 60.00
otbn_tl_intg_err 32.000s 209.342us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 38.000s 241.306us 19 20 95.00
V2S prim_fsm_check otbn_sec_cm 4.150m 2.143ms 3 5 60.00
V2S prim_count_check otbn_sec_cm 4.150m 2.143ms 3 5 60.00
V2S sec_cm_mem_scramble otbn_smoke 14.000s 139.154us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 14.000s 33.250us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 10.000s 18.773us 2 10 20.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 32.000s 209.342us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 21.000s 128.387us 18 60 30.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 10.000s 18.773us 2 10 20.00
otbn_dmem_err 14.000s 33.250us 0 15 0.00
otbn_zero_state_err_urnd 12.000s 266.413us 1 5 20.00
otbn_illegal_mem_acc 9.000s 89.282us 5 5 100.00
otbn_sec_cm 4.150m 2.143ms 3 5 60.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 4.150m 2.143ms 3 5 60.00
V2S sec_cm_scramble_key_sideload otbn_single 1.883m 458.103us 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 10.000s 18.773us 2 10 20.00
otbn_dmem_err 14.000s 33.250us 0 15 0.00
otbn_zero_state_err_urnd 12.000s 266.413us 1 5 20.00
otbn_illegal_mem_acc 9.000s 89.282us 5 5 100.00
otbn_sec_cm 4.150m 2.143ms 3 5 60.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 4.150m 2.143ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 21.000s 128.387us 18 60 30.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 10.000s 18.773us 2 10 20.00
otbn_dmem_err 14.000s 33.250us 0 15 0.00
otbn_zero_state_err_urnd 12.000s 266.413us 1 5 20.00
otbn_illegal_mem_acc 9.000s 89.282us 5 5 100.00
otbn_sec_cm 4.150m 2.143ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 4.150m 2.143ms 3 5 60.00
V2S sec_cm_data_reg_sw_sca otbn_single 1.883m 458.103us 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 15.000s 57.372us 1 12 8.33
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 9.000s 185.543us 4 5 80.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 1.150m 888.092us 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 1.150m 888.092us 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 15.000s 55.100us 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 4.150m 2.143ms 3 5 60.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 4.150m 2.143ms 3 5 60.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 13.000s 85.647us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 4.150m 2.143ms 3 5 60.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 4.150m 2.143ms 3 5 60.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 20.000s 88.810us 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 20.000s 88.810us 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 19.000s 36.362us 5 7 71.43
V2S sec_cm_data_mem_sec_wipe otbn_single 1.883m 458.103us 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 1.883m 458.103us 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 1.883m 458.103us 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 7.867m 3.208ms 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 1.883m 458.103us 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 1.883m 458.103us 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 21.000s 63.042us 0 5 0.00
V2S sec_cm_key_sideload otbn_single 1.883m 458.103us 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 4.150m 2.143ms 3 5 60.00
V2S TOTAL 72 163 44.17
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 6.667m 2.665ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 296 585 50.60

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
94.38 97.96 73.64 97.16 82.02 63.52 87.18 80.68 98.29

Failure Buckets