ROM_CTRL/32KB Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.530s	2.215ms	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	7.470s	177.369us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	9.400s	536.507us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.750s	168.707us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.700s	172.124us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.280s	174.777us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	9.400s	536.507us	20	20	100.00
		rom_ctrl_csr_aliasing	6.700s	172.124us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	7.630s	536.135us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.030s	124.327us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.340s	140.843us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	30.280s	4.192ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	12.660s	546.476us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	8.210s	532.130us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.550s	159.760us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.550s	159.760us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	7.470s	177.369us	5	5	100.00
		rom_ctrl_csr_rw	9.400s	536.507us	20	20	100.00
		rom_ctrl_csr_aliasing	6.700s	172.124us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.140s	310.716us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	7.470s	177.369us	5	5	100.00
		rom_ctrl_csr_rw	9.400s	536.507us	20	20	100.00
		rom_ctrl_csr_aliasing	6.700s	172.124us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.140s	310.716us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.281m	3.446ms	14	20	70.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	49.320s	3.167ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	5.162m	3.911ms	3	5	60.00
		rom_ctrl_tl_intg_err	1.188m	590.672us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	5.162m	3.911ms	3	5	60.00
V2S	prim_count_check	rom_ctrl_sec_cm	5.162m	3.911ms	3	5	60.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.281m	3.446ms	14	20	70.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.281m	3.446ms	14	20	70.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.281m	3.446ms	14	20	70.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.281m	3.446ms	14	20	70.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.281m	3.446ms	14	20	70.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	5.162m	3.911ms	3	5	60.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	5.162m	3.911ms	3	5	60.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.530s	2.215ms	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.530s	2.215ms	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.530s	2.215ms	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.188m	590.672us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.281m	3.446ms	14	20	70.00
		rom_ctrl_kmac_err_chk	12.660s	546.476us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.281m	3.446ms	14	20	70.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.281m	3.446ms	14	20	70.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.281m	3.446ms	14	20	70.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	49.320s	3.167ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	5.162m	3.911ms	3	5	60.00
V2S		TOTAL			57	65	87.69
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	11.419m	11.528ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			258	266	96.99

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.14	99.59	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 6 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 6 failures.
  - 2.rom_ctrl_corrupt_sig_fatal_chk.115213843574666479782921958800481779121388173657124614752870890495503688264849
    Line 75, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 717272098 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 717272098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.rom_ctrl_corrupt_sig_fatal_chk.6407370698277258464470533511910529795821549992811269638803349831380850981107
    Line 90, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 2867973685 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 2867973685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

Test rom_ctrl_sec_cm has 1 failures.

1.rom_ctrl_sec_cm.12157171615377175369903729744439710693098253472769391082600603312501412957722
Line 217, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 4220769ps failed at 4220769ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  Starting assertion attempts at time 5905372ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
  Starting assertion attempts at time 5905372ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))

Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

Test rom_ctrl_sec_cm has 1 failures.

4.rom_ctrl_sec_cm.8271366642279918059342394964848466556063215772367590996812287371850671497756
Line 234, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 93256461ps failed at 93256461ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 93256461ps failed at 93256461ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'