ROM_CTRL/64KB Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	11.260s	607.612us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.370s	1.335ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	12.090s	294.087us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	9.520s	306.301us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	11.900s	289.398us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	13.170s	4.155ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	12.090s	294.087us	20	20	100.00
		rom_ctrl_csr_aliasing	11.900s	289.398us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	10.810s	1.071ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.860s	1.018ms	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	11.930s	304.423us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	1.256m	44.047ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	17.950s	1.058ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	15.940s	4.312ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.760s	6.596ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.760s	6.596ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.370s	1.335ms	5	5	100.00
		rom_ctrl_csr_rw	12.090s	294.087us	20	20	100.00
		rom_ctrl_csr_aliasing	11.900s	289.398us	5	5	100.00
		rom_ctrl_same_csr_outstanding	13.010s	1.104ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.370s	1.335ms	5	5	100.00
		rom_ctrl_csr_rw	12.090s	294.087us	20	20	100.00
		rom_ctrl_csr_aliasing	11.900s	289.398us	5	5	100.00
		rom_ctrl_same_csr_outstanding	13.010s	1.104ms	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.060m	6.725ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	59.440s	2.100ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	5.036m	452.962us	2	5	40.00
		rom_ctrl_tl_intg_err	2.403m	2.093ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	5.036m	452.962us	2	5	40.00
V2S	prim_count_check	rom_ctrl_sec_cm	5.036m	452.962us	2	5	40.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.060m	6.725ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.060m	6.725ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.060m	6.725ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.060m	6.725ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.060m	6.725ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	5.036m	452.962us	2	5	40.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	5.036m	452.962us	2	5	40.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	11.260s	607.612us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	11.260s	607.612us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	11.260s	607.612us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.403m	2.093ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.060m	6.725ms	20	20	100.00
		rom_ctrl_kmac_err_chk	17.950s	1.058ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.060m	6.725ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.060m	6.725ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.060m	6.725ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	59.440s	2.100ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	5.036m	452.962us	2	5	40.00
V2S		TOTAL			62	65	95.38
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.938m	11.184ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			263	266	98.87

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.14	99.59	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 2 failures:

  • Test rom_ctrl_sec_cm has 2 failures.

    • 1.rom_ctrl_sec_cm.398717175066671605405822336606330108441914725240816409261746785084249330875
      Line 176, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 33424513ps failed at 33424513ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 33424513ps failed at 33424513ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • 2.rom_ctrl_sec_cm.24855213771843220377701889010301842738505584175777088065698980472448879477739
      Line 183, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 18727426ps failed at 18727426ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 18727426ps failed at 18727426ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.76302338572415909744302468664384468976095937996659183803575326150313980890805
      Line 174, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 9118380ps failed at 9118380ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 9130575ps failed at 9130575ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'