RV_TIMER Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.860s	175.361us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.900s	22.144us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.900s	12.142us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.530s	276.340us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.990s	29.556us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.470s	128.147us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.900s	12.142us	20	20	100.00
		rv_timer_csr_aliasing	0.990s	29.556us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	9.180s	13.084ms	1	20	5.00
V2	disabled	rv_timer_disabled	3.780s	3.076ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	9.643m	866.087ms	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	9.643m	866.087ms	10	10	100.00
V2	stress	rv_timer_stress_all	9.060s	5.705ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.860s	12.440us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.850s	27.714us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.980s	183.971us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.980s	183.971us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.900s	22.144us	5	5	100.00
		rv_timer_csr_rw	0.900s	12.142us	20	20	100.00
		rv_timer_csr_aliasing	0.990s	29.556us	5	5	100.00
		rv_timer_same_csr_outstanding	1.010s	133.722us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.900s	22.144us	5	5	100.00
		rv_timer_csr_rw	0.900s	12.142us	20	20	100.00
		rv_timer_csr_aliasing	0.990s	29.556us	5	5	100.00
		rv_timer_same_csr_outstanding	1.010s	133.722us	20	20	100.00
V2		TOTAL			191	210	90.95
V2S	tl_intg_err	rv_timer_sec_cm	1.290s	337.641us	5	5	100.00
		rv_timer_tl_intg_err	1.710s	1.594ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.710s	1.594ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	1.360s	62.879us	2	10	20.00
V3	max_value	rv_timer_max	1.220s	43.278us	0	10	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.117m	29.246ms	14	20	70.00
V3		TOTAL			16	40	40.00
		TOTAL			307	350	87.71

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.77	100.00	100.00	78.66	--	100.00	96.82	99.12

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 27 failures:
- Test rv_timer_min has 8 failures.
  - 0.rv_timer_min.36987052655334697451808572339808970383737813981588332795665985063774410738958
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 223879470 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7b85ab04) == 0x1
  UVM_INFO @ 223879470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_min.37055386170652164452931899650593402242235983326314398447514044129258582942200
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 231420760 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x28117b04) == 0x1
  UVM_INFO @ 231420760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.
- Test rv_timer_random_reset has 19 failures.
  - 0.rv_timer_random_reset.76676088688887038820439930551229366631688856345304437551489975132805351391096
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1021823600 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3e797104) == 0x1
  UVM_INFO @ 1021823600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_random_reset.18068957559775865402294171269701561096836486643296845143792272155430259918207
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 176515549 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xeefc8104) == 0x1
  UVM_INFO @ 176515549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 9 failures:
- Test rv_timer_max has 9 failures.
  - 0.rv_timer_max.73010216495355598502712484194350343825406157703778972803809464732686625475834
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @  43277629 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  43277629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_max.43562402985254447437338895172621505220548430191505101527564508075309679143219
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
```
  UVM_ERROR @  90245808 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  90245808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test rv_timer_stress_all_with_rand_reset has 4 failures.

3.rv_timer_stress_all_with_rand_reset.3791891647465053764380687800786387696185696165908789530740573966942877288719
Line 106, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 989859137 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 989859137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.rv_timer_stress_all_with_rand_reset.44380614254913503564867419723222308295851426004431275365273944948349266081130
Line 145, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/5.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 877014514 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 877014514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 2 failures:
- Test rv_timer_stress_all_with_rand_reset has 2 failures.
  - 1.rv_timer_stress_all_with_rand_reset.60667323797737132215873292812537813359740599680000562602298999015462717631759
    Line 76, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  14953753 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @  14953753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 14.rv_timer_stress_all_with_rand_reset.45816725448978940013085598203151272483979398950842568307834275572984182537154
    Line 118, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/14.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 331296330 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 331296330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rv_timer_scoreboard.sv:365) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) has 1 failures:
- Test rv_timer_max has 1 failures.
  - 5.rv_timer_max.33023572346908798656584141604821439330336273908726557887049558168497713782305
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/5.rv_timer_max/latest/run.log
```
  UVM_ERROR @ 851616249 ps: (rv_timer_scoreboard.sv:365) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
  UVM_INFO @ 851616249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```