SPI_DEVICE/1R1W Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.891m	77.266ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.580s	152.549us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.780s	88.139us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	31.430s	30.194ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	18.390s	327.609us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.080s	963.863us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.780s	88.139us	20	20	100.00
		spi_device_csr_aliasing	18.390s	327.609us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.070s	23.725us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.550s	234.769us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.200s	62.162us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	1.358us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.730s	3.058us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	10.740s	334.681us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.740s	334.681us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	23.400s	6.830ms	50	50	100.00
		spi_device_tpm_sts_read	1.510s	212.908us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	44.300s	7.534ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	41.580s	25.749ms	50	50	100.00
		spi_device_flash_all	5.509m	107.869ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	29.900s	19.695ms	50	50	100.00
		spi_device_flash_all	5.509m	107.869ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	29.900s	19.695ms	50	50	100.00
		spi_device_flash_all	5.509m	107.869ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.509m	107.869ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	23.550s	12.805ms	50	50	100.00
		spi_device_flash_all	5.509m	107.869ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	23.550s	12.805ms	50	50	100.00
		spi_device_flash_all	5.509m	107.869ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	23.550s	12.805ms	50	50	100.00
		spi_device_flash_all	5.509m	107.869ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	23.550s	12.805ms	50	50	100.00
		spi_device_flash_all	5.509m	107.869ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	23.550s	12.805ms	50	50	100.00
		spi_device_flash_all	5.509m	107.869ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	41.990s	10.470ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.077m	14.893ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.077m	14.893ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.077m	14.893ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.197m	5.028ms	50	50	100.00
		spi_device_read_buffer_direct	16.480s	6.327ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.077m	14.893ms	50	50	100.00
		spi_device_flash_all	5.509m	107.869ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.509m	107.869ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.509m	107.869ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	33.580s	17.978ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	33.580s	17.978ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.891m	77.266ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.513m	337.829ms	50	50	100.00
V2	stress_all	spi_device_stress_all	11.011m	89.649ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.140s	19.193us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.160s	15.102us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.230s	1.373ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.230s	1.373ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.580s	152.549us	5	5	100.00
		spi_device_csr_rw	2.780s	88.139us	20	20	100.00
		spi_device_csr_aliasing	18.390s	327.609us	5	5	100.00
		spi_device_same_csr_outstanding	4.760s	814.450us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.580s	152.549us	5	5	100.00
		spi_device_csr_rw	2.780s	88.139us	20	20	100.00
		spi_device_csr_aliasing	18.390s	327.609us	5	5	100.00
		spi_device_same_csr_outstanding	4.760s	814.450us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	1.440s	164.703us	5	5	100.00
		spi_device_tl_intg_err	16.950s	1.206ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.950s	1.206ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.869m	550.583ms	49	50	98.00
		TOTAL			1129	1151	98.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.62	99.12	96.56	71.19	89.36	98.42	94.43	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.45314075718824157877659459911756242701244676152672119730820905092157493357665
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1811450 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[8])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1811450 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1811450 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[904])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.114979984923290849990650493561354679028538019268747476402105932422184130047422
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @  10563597 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[100])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @  10563597 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @  10563597 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[996])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.16191700514315323189813324314338397274957128985707844363216833609427116359642
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @    871166 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7d9064 [11111011001000001100100] vs 0x0 [0])
  UVM_ERROR @    918166 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xef7441 [111011110111010001000001] vs 0x0 [0])
  UVM_ERROR @    932166 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbbe459 [101110111110010001011001] vs 0x0 [0])
  UVM_ERROR @    964166 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa82d5b [101010000010110101011011] vs 0x0 [0])
  UVM_ERROR @   1053166 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x72e463 [11100101110010001100011] vs 0x0 [0])

Job timed out after * minutes has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 43.spi_device_flash_mode_ignore_cmds.77408679634446394696312586552262533185123211086601592271141917050748699844236
    Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job timed out after 60 minutes
```