SPI_HOST Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.717m	6.017ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	28.698us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	59.905us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	105.310us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	23.856us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	78.085us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	59.905us	20	20	100.00
		spi_host_csr_aliasing	2.000s	23.856us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	15.723us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	137.159us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	3.000s	143.601us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	52.000s	5.069ms	50	50	100.00
		spi_host_error_cmd	2.000s	45.388us	50	50	100.00
		spi_host_event	11.517m	23.517ms	50	50	100.00
V2	clock_rate	spi_host_speed	6.000s	503.976us	50	50	100.00
V2	speed	spi_host_speed	6.000s	503.976us	50	50	100.00
V2	chip_select_timing	spi_host_speed	6.000s	503.976us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	1.400m	3.565ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	99.667us	50	50	100.00
V2	cpol_cpha	spi_host_speed	6.000s	503.976us	50	50	100.00
V2	full_cycle	spi_host_speed	6.000s	503.976us	50	50	100.00
V2	duplex	spi_host_smoke	1.717m	6.017ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.717m	6.017ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.033m	5.836ms	50	50	100.00
V2	spien	spi_host_spien	4.300m	25.134ms	48	50	96.00
V2	stall	spi_host_status_stall	23.500m	139.944ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	41.000s	8.068ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	52.000s	5.069ms	50	50	100.00
V2	alert_test	spi_host_alert_test	7.000s	37.452us	50	50	100.00
V2	intr_test	spi_host_intr_test	2.000s	160.577us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	3.000s	662.472us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	3.000s	662.472us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	28.698us	5	5	100.00
		spi_host_csr_rw	2.000s	59.905us	20	20	100.00
		spi_host_csr_aliasing	2.000s	23.856us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	15.961us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	28.698us	5	5	100.00
		spi_host_csr_rw	2.000s	59.905us	20	20	100.00
		spi_host_csr_aliasing	2.000s	23.856us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	15.961us	20	20	100.00
V2		TOTAL			686	690	99.42
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	2.187ms	20	20	100.00
		spi_host_sec_cm	2.000s	162.291us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	2.187ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	15.317m	119.672ms	7	10	70.00
		TOTAL			833	840	99.17

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.10	96.82	93.35	98.69	94.35	73.07	100.00	95.21	90.42

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test spi_host_upper_range_clkdiv has 2 failures.
  - 5.spi_host_upper_range_clkdiv.73491735284893441953596075298310770405709104780031298664021478944177477461155
    Line 149, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.spi_host_upper_range_clkdiv.26573899294797847148521479295055806919212792687872003242307367233378504756202
    Line 138, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 2 failures:

Test spi_host_spien has 2 failures.

18.spi_host_spien.1281537266681227467292452314665233490888932733845049037792897982272382189332
Line 378, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/18.spi_host_spien/latest/run.log

  UVM_FATAL @ 10293001237 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0xcb107594, Comparison=CompareOpEq, exp_data=0x0, call_count=76
  UVM_INFO @ 10293001237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.spi_host_spien.15950077393954917062173456795404081224661517824677469255664785193658155935845
Line 376, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/48.spi_host_spien/latest/run.log

  UVM_FATAL @ 10219986693 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x593dd894, Comparison=CompareOpEq, exp_data=0x0, call_count=66
  UVM_INFO @ 10219986693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 1.spi_host_upper_range_clkdiv.5590181443191330466996585036916100264546828020258712615966242459905053829793
    Line 200, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 119671562495 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 50000000ns spi_host_reg_block.status.active (addr=0x356ccb54, Comparison=CompareOpEq, exp_data=0x0, call_count=29
  UVM_INFO @ 119671562495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.status.rxfull reset value: * has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 3.spi_host_status_stall.107052553562088013034873210850857898442299104278572827616104785653641406446314
    Line 2682, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_status_stall/latest/run.log
```
  UVM_ERROR @ 202885565 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.rxfull reset value: 0x0
  UVM_INFO @ 202885565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

Test spi_host_status_stall has 1 failures.

43.spi_host_status_stall.44639699076840773925357455304356670860646296889950998050957864009147230146351
Line 10084, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/43.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 139944416829 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 139944416829 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=139944417000 ps
  UVM_INFO @ 139944416829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---