SRAM_CTRL/MAIN Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.819m	3.216ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.060s	56.383us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.060s	17.663us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.770s	599.992us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.110s	21.379us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	7.290s	5.051ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.060s	17.663us	20	20	100.00
		sram_ctrl_csr_aliasing	1.110s	21.379us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.698m	51.179ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.932m	92.695ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	28.847m	137.650ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.256m	83.315ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	45.040m	861.825ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	16.968m	62.430ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.201m	18.999ms	50	50	100.00
V2	executable	sram_ctrl_executable	21.326m	29.877ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.534m	4.235ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.560m	19.836ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.776m	804.317us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.584m	4.590ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.667m	1.847ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	23.842m	21.434ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.040s	1.351ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.966h	110.323ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.100s	139.071us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.070s	967.118us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.070s	967.118us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.060s	56.383us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	17.663us	20	20	100.00
		sram_ctrl_csr_aliasing	1.110s	21.379us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.150s	86.560us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.060s	56.383us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	17.663us	20	20	100.00
		sram_ctrl_csr_aliasing	1.110s	21.379us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.150s	86.560us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.124m	29.297ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.140s	35.857us	0	5	0.00
		sram_ctrl_tl_intg_err	4.410s	1.266ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.140s	35.857us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.410s	1.266ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	23.842m	21.434ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	23.842m	21.434ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.060s	17.663us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	21.326m	29.877ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	21.326m	29.877ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	21.326m	29.877ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.201m	18.999ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	12.140s	13.237ms	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.124m	29.297ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	12.230s	13.186ms	33	50	66.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.819m	3.216ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.819m	3.216ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	21.326m	29.877ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.140s	35.857us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.201m	18.999ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.140s	35.857us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.140s	35.857us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.819m	3.216ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.140s	35.857us	0	5	0.00
V2S		TOTAL			117	145	80.69
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.696m	10.965ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1161	1190	97.56

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.61	99.11	92.78	85.46	100.00	97.77	95.83	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 17 failures:
- Test sram_ctrl_readback_err has 17 failures.
  - 3.sram_ctrl_readback_err.43090847231108952429034446686962737198835295900051398198250717308928219303181
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 658729298 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x30) != exp (0x1)
  UVM_INFO @ 658729298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.sram_ctrl_readback_err.114979865146478458649929755702594791050395976445991250004974776359795431941077
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/6.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 3285384925 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6d) != exp (0x6e)
  UVM_INFO @ 3285384925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 15 more failures.
Offending 'reqfifo_rvalid' has 5 failures:
- Test sram_ctrl_mubi_enc_err has 5 failures.
  - 25.sram_ctrl_mubi_enc_err.57282230328654948109935105361995064333295305656884687044339068210012208160241
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/25.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 1368999333 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 1368999333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 27.sram_ctrl_mubi_enc_err.4304507537872154654908514195132037198838270513714293634890105934560619351886
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/27.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 2667978726 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 2667978726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:
- Test sram_ctrl_sec_cm has 3 failures.
  - 0.sram_ctrl_sec_cm.51102913885292607244551615061542934424913277344048840391106499642030055643665
    Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @  35857214 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  35857214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.sram_ctrl_sec_cm.26979234687754966961630035871932795471715536331803201023492913386302937571946
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   3356523 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   3356523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
Offending '(depth_o <= *'(Depth))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 3.sram_ctrl_sec_cm.102810218883041116611881634654910449510007191529446277660120124896671342431856
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(depth_o <= 2'(Depth))'
  UVM_ERROR @   2028989 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
  UVM_INFO @   2028989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

Test sram_ctrl_sec_cm has 1 failures.

4.sram_ctrl_sec_cm.11057961129150409123241046053669218892776826862258556580544499190596001606645
Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  UVM_ERROR @   4194628 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   4194628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1142) [sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 9.sram_ctrl_stress_all_with_rand_reset.41543850629685803176840853833578541981881266769286080167668362070652045028407
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 325317352 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 325317352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3548) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_mubi_enc_err has 1 failures.

40.sram_ctrl_mubi_enc_err.69384585790118583705862625799107110644478039682474318393431661501052204236730
Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/40.sram_ctrl_mubi_enc_err/latest/run.log

  UVM_ERROR @ 2737911589 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3548) { a_addr: 'h51cf7b0c  a_data: 'h18  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h9b  a_opcode: 'h1  a_user: 'h24a84  d_param: 'h0  d_source: 'h9b  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2737911589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---