SRAM_CTRL/RET Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: `c5877ed`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.078m	736.019us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.000s	57.532us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.080s	14.845us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.510s	118.775us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.100s	56.572us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.200s	46.973us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.080s	14.845us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	56.572us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.490s	2.706ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.290s	2.321ms	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	16.716m	14.411ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.758m	46.835ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.584m	17.178ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	20.822m	15.014ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	12.150s	12.185ms	50	50	100.00
V2	executable	sram_ctrl_executable	24.558m	18.062ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.702m	425.051us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.508m	90.886ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.138m	536.528us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.829m	153.876us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.733m	292.522us	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.284m	172.363ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.270s	51.314us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.015h	52.147ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.060s	229.362us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.730s	263.819us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.730s	263.819us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.000s	57.532us	5	5	100.00
		sram_ctrl_csr_rw	1.080s	14.845us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	56.572us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.170s	72.165us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.000s	57.532us	5	5	100.00
		sram_ctrl_csr_rw	1.080s	14.845us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	56.572us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.170s	72.165us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.520s	3.461ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.160s	25.768us	0	5	0.00
		sram_ctrl_tl_intg_err	4.550s	4.387ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.160s	25.768us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.550s	4.387ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.284m	172.363ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	22.284m	172.363ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.080s	14.845us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	24.558m	18.062ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	24.558m	18.062ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	24.558m	18.062ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	12.150s	12.185ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.610s	347.045us	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.520s	3.461ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.700s	52.431us	31	50	62.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.078m	736.019us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.078m	736.019us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	24.558m	18.062ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.160s	25.768us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	12.150s	12.185ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.160s	25.768us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.160s	25.768us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.078m	736.019us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.160s	25.768us	0	5	0.00
V2S		TOTAL			115	145	79.31
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	9.388m	3.986ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1158	1190	97.31

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.64	99.07	92.90	85.37	100.00	97.98	95.79	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 19 failures:
- Test sram_ctrl_readback_err has 19 failures.
  - 0.sram_ctrl_readback_err.60441031047419089744754456477610603761351917750066086388694121367701682127199
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  87459422 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4f) != exp (0x22)
  UVM_INFO @  87459422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.sram_ctrl_readback_err.48284609916473782675034949835969393327759081451868344205104083420753518906752
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 100144970 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5b) != exp (0x6)
  UVM_INFO @ 100144970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.
Offending 'reqfifo_rvalid' has 5 failures:
- Test sram_ctrl_mubi_enc_err has 5 failures.
  - 8.sram_ctrl_mubi_enc_err.71329693104738373090939858745025857635882626317480036337161244456006132721395
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  32814368 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  32814368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 15.sram_ctrl_mubi_enc_err.9852770974254638533212291334391805739885028030545355902912656914279955834144
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  40386139 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  40386139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

Test sram_ctrl_sec_cm has 2 failures.

0.sram_ctrl_sec_cm.12909711695994588285052190147515643445064587758038080068132968274902072352935
Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @   6005460 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   6005460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.sram_ctrl_sec_cm.46378147565636446449733709246873042572156461586410300631756651563271885695983
Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @  25767916 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  25767916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(!$isunknown(rdata_o))' has 2 failures:
- Test sram_ctrl_sec_cm has 2 failures.
  - 2.sram_ctrl_sec_cm.95942746423580868858205232207533676962309265756914176629255480482872814810704
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   1562561 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1562561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.sram_ctrl_sec_cm.68782267921807093812305048586160370400060894024656565959148124529987373489286
    Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   5635629 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   5635629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 12.sram_ctrl_csr_mem_rw_with_rand_reset.96795486905142878001093037919485842760747815132315987851032092720909449054971
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  27099021 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  27099021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 14.sram_ctrl_csr_mem_rw_with_rand_reset.68894758708421612599809253970867227943923868451865232877191245913447598451854
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 324120211 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @ 324120211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

Test sram_ctrl_sec_cm has 1 failures.

1.sram_ctrl_sec_cm.67558490605364354849934844365661507333133093360583818260495163233794094676589
Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  UVM_ERROR @   3739257 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   3739257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4880) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_mubi_enc_err has 1 failures.

23.sram_ctrl_mubi_enc_err.105442062359417268694651181669613020171035475069578942791137955475153696854360
Line 100, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mubi_enc_err/latest/run.log

  UVM_ERROR @ 183347437 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4880) { a_addr: 'hab6c28c0  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hae  a_opcode: 'h4  a_user: 'h245aa  d_param: 'h0  d_source: 'hae  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 183347437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---