CHIP Simulation Results

Friday September 26 2025 17:02:09 UTC

GitHub Revision: c5877ed

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.381m		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.381m		0	5	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.658m		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.530m		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.313m		0	5	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.972m	4.683ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.972m	4.683ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.972m	4.683ms	3	3	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	52.930s	10.380us	0	3	0.00
		chip_sw_example_manufacturer	28.386s		0	3	0.00
		chip_sw_example_concurrency	6.020m	4.245ms	3	3	100.00
		chip_sw_uart_smoketest_signed	18.217s		0	3	0.00
V1	csr_bit_bash	chip_csr_bit_bash	14.110s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	14.590s		0	3	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	14.590s		0	3	0.00
V1	xbar_smoke	xbar_smoke	38.440s	72.525us	100	100	100.00
V1		TOTAL			106	156	67.95
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.248m		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	14.016m	8.941ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	6.774m	4.826ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	56.326s		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	50.258s		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.380m		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.075m		0	3	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.250s		0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.250s		0	10	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.905m		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.752m		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	3.022m		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	3.022m		0	6	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	4.443m	4.366ms	0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	6.234m	5.458ms	0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	9.708m	15.024ms	0	3	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	18.640s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	19.002s		0	3	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	19.584m	18.085ms	2	3	66.67
V2	chip_sw_timer	chip_sw_rv_timer_irq	8.948m	6.914ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	41.543m	18.018ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	41.543m	18.018ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	17.527s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.087m	3.747ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.087m	3.747ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	11.743m	18.019ms	0	5	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	7.013m	5.842ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	10.427m	5.954ms	3	3	100.00
		chip_sw_aes_idle	5.533m	4.962ms	3	3	100.00
		chip_sw_hmac_enc_idle	7.548m	6.053ms	3	3	100.00
		chip_sw_kmac_idle	4.905m	3.364ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	21.320m	12.027ms	0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	22.050m	12.018ms	0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	21.674m	12.019ms	0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	18.777m	12.027ms	0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	15.578s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	22.743s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	20.452s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	19.402s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.536s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	20.373s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	19.776s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	15.578s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	22.743s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	20.452s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	19.402s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.536s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	20.373s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	19.776s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	24.312s		0	3	0.00
		chip_sw_aes_enc_jitter_en	50.640s	10.360us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	54.050s	10.320us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	57.030s	10.360us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	55.550s	10.260us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	19.344s		0	3	0.00
		chip_sw_clkmgr_jitter	6.331m	5.693ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	5.812m	5.440ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	19.579s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.073m	10.260us	0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	50.080s	10.220us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	47.800s	10.240us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	52.970s	10.300us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	53.350s	10.140us	0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	19.358s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	18.079s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	19.977s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	18.784s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	38.299m	16.191ms	87	100	87.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	13.346m	11.031ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	6.087m	3.747ms	0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	18.488s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	13.346m	11.031ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	20.641s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	20.940s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	18.809s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	22.422s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	20.021s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	38.299m	16.191ms	87	100	87.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	9.708m	15.024ms	0	3	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	48.012m	20.018ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	11.599m	9.274ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.810m	9.251ms	0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	6.226m	3.778ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	38.299m	16.191ms	87	100	87.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	17.874s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	19.563s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	38.299m	16.191ms	87	100	87.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	18.182s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.810m	9.251ms	0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	19.984s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	21.238s		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	18.770s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	18.500s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.661s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	19.325s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	19.563s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	27.017s		0	15	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	19.370s		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	27.017s		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	27.017s		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	27.017s		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	11.228m	7.436ms	0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	19.580s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	20.193s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	19.594s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	16.981s		0	3	0.00
		chip_sw_lc_ctrl_transition	27.017s		0	15	0.00
		chip_sw_keymgr_dpe_key_derivation	9.067m	6.898ms	0	3	0.00
		chip_sw_rom_ctrl_integrity_check	14.298m	13.772ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	19.033s		0	3	0.00
		chip_prim_tl_access	34.014m	27.775ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	15.578s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	22.743s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	20.452s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	19.402s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	19.536s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	20.373s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	19.776s		0	3	0.00
		chip_rv_dm_lc_disabled	19.584m	18.085ms	2	3	66.67
V2	chip_sw_aes_enc	chip_sw_aes_enc	7.218m	5.066ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	50.640s	10.360us	0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	7.443m	5.581ms	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.533m	4.962ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	7.641m	5.816ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	54.050s	10.320us	0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	7.548m	6.053ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	7.427m	5.387ms	3	3	100.00
		chip_sw_kmac_mode_kmac	7.522m	4.898ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	55.550s	10.260us	0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	9.067m	6.898ms	0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	27.017s		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	50.460s	10.280us	0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	7.796m	4.773ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.905m	3.364ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	17.736s		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	17.736s		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	17.437s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	6.656m	5.055ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	18.052s		0	3	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	9.067m	6.898ms	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	57.030s	10.360us	0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	18.171s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	24.312s		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	10.427m	5.954ms	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	10.427m	5.954ms	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	10.427m	5.954ms	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	11.150m	5.744ms	3	3	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	14.298m	13.772ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	14.298m	13.772ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	15.904m	8.873ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	19.344s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	19.033s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	38.299m	16.191ms	87	100	87.00
		chip_sw_data_integrity_escalation	3.022m		0	6	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	27.017s		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	11.150m	5.744ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	9.067m	6.898ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	15.904m	8.873ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	7.362m	5.761ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	11.150m	5.744ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	9.067m	6.898ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	15.904m	8.873ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	7.362m	5.761ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	27.017s		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	18.857s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	19.370s		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	19.580s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	20.193s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	19.594s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	16.981s		0	3	0.00
		chip_sw_lc_ctrl_transition	27.017s		0	15	0.00
		chip_prim_tl_access	34.014m	27.775ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	34.014m	27.775ms	3	3	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	25.762s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	25.252s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	18.079s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	24.312s		0	3	0.00
		chip_sw_aes_enc_jitter_en	50.640s	10.360us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	54.050s	10.320us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	57.030s	10.360us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	55.550s	10.260us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	19.344s		0	3	0.00
		chip_sw_clkmgr_jitter	6.331m	5.693ms	3	3	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	11.637m	6.400ms	3	3	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	11.637m	6.400ms	3	3	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	6.475m	5.046ms	0	3	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	6.391m	5.430ms	0	3	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	6.740m	5.344ms	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	11.287m	6.770ms	0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.994m	4.155ms	3	3	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	7.300m	5.025ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	7.362m	5.761ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	48.012m	20.018ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	48.012m	20.018ms	0	3	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	6.665m	4.239ms	3	3	100.00
		chip_sw_aon_timer_smoketest	8.050m	5.259ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.769m	5.338ms	3	3	100.00
		chip_sw_csrng_smoketest	6.408m	5.311ms	3	3	100.00
		chip_sw_gpio_smoketest	6.210m	3.698ms	3	3	100.00
		chip_sw_hmac_smoketest	7.997m	5.865ms	3	3	100.00
		chip_sw_kmac_smoketest	6.979m	4.754ms	3	3	100.00
		chip_sw_otbn_smoketest	7.837m	5.400ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.334m	4.563ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.958m	4.243ms	3	3	100.00
		chip_sw_rv_timer_smoketest	9.190m	6.824ms	3	3	100.00
		chip_sw_rstmgr_smoketest	6.439m	5.603ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	6.765m	4.690ms	3	3	100.00
		chip_sw_uart_smoketest	6.588m	4.419ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	15.381s		0	3	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	18.217s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.248m		0	3	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	19.117s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.755m	4.705ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.927m	4.667ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	5.973m	4.882ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	7.514m	6.079ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	29.244s		0	3	0.00
		chip_rv_dm_lc_disabled	19.584m	18.085ms	2	3	66.67
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	19.212s		0	3	0.00
		chip_sw_lc_walkthrough_prod	19.214s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	25.163s		0	3	0.00
		chip_sw_lc_walkthrough_rma	22.089s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	29.244s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	17.863s		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	21.051s		0	3	0.00
		rom_volatile_raw_unlock	17.584s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	18.807s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.978m		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.287m		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	5.171m	5.194ms	1	30	3.33
V2	tl_d_illegal_access	chip_tl_errors	5.171m	5.194ms	1	30	3.33
V2	tl_d_outstanding_access	chip_csr_aliasing	14.590s		0	3	0.00
		chip_same_csr_outstanding	14.230s		0	3	0.00
V2	tl_d_partial_access	chip_csr_aliasing	14.590s		0	3	0.00
		chip_same_csr_outstanding	14.230s		0	3	0.00
V2	xbar_base_random_sequence	xbar_random	5.694m	552.871us	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	15.350s	12.873us	100	100	100.00
		xbar_smoke_large_delays	9.168m	2.623ms	100	100	100.00
		xbar_smoke_slow_rsp	10.097m	2.087ms	100	100	100.00
		xbar_random_zero_delays	2.397m	75.774us	100	100	100.00
		xbar_random_large_delays	37.460m	13.082ms	100	100	100.00
		xbar_random_slow_rsp	57.640m	14.772ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	2.941m	216.162us	100	100	100.00
		xbar_error_and_unmapped_addr	3.010m	243.014us	100	100	100.00
V2	xbar_error_cases	xbar_error_random	5.058m	550.565us	100	100	100.00
		xbar_error_and_unmapped_addr	3.010m	243.014us	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	7.953m	931.409us	100	100	100.00
		xbar_access_same_device_slow_rsp	58.536m	16.496ms	64	100	64.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	3.626m	443.693us	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	31.875m	3.753ms	100	100	100.00
		xbar_stress_all_with_error	35.769m	4.729ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	53.013m	4.809ms	100	100	100.00
		xbar_stress_all_with_reset_error	54.953m	8.027ms	99	100	99.00
V2	rom_e2e_smoke	rom_e2e_smoke	19.266s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	18.718s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	17.243s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	18.804s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	14.298s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	16.516s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	17.926s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	16.304s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	13.023s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	15.670s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	14.975s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.995s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	1.030m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	42.949s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.353m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.067m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	58.784s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.379m		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.378m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	56.173s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	47.707s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	44.426s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.085m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	48.289s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	1.166m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	1.087m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	59.464s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	49.640s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.774s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.630s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	15.330s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	15.788s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.451s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	18.119s		0	3	0.00
		rom_e2e_asm_init_dev	15.600s		0	3	0.00
		rom_e2e_asm_init_prod	16.697s		0	3	0.00
		rom_e2e_asm_init_prod_end	17.285s		0	3	0.00
		rom_e2e_asm_init_rma	18.324s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	18.621s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	18.046s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	18.269s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	18.393s		0	3	0.00
V2		TOTAL			1885	2429	77.60
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.606m	5.684ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	5.922m	5.402ms	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.351s		0	1	0.00
		rom_e2e_jtag_debug_dev	15.453s		0	1	0.00
		rom_e2e_jtag_debug_rma	15.812s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	19.790s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	38.299m	16.191ms	87	100	87.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	27.243s		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	26.213m	13.015ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	16.415s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	19.276s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.351s		0	1	0.00
		rom_e2e_jtag_debug_dev	15.453s		0	1	0.00
		rom_e2e_jtag_debug_rma	15.812s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	14.717s		0	1	0.00
		rom_e2e_jtag_inject_dev	14.656s		0	1	0.00
		rom_e2e_jtag_inject_rma	15.030s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	18.284s		0	3	0.00
V3		TOTAL			1	20	5.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	33.766m	15.513ms	3	3	100.00
		chip_sw_entropy_src_kat_test	5.400m	4.683ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	5.031m	4.939ms	3	3	100.00
		chip_plic_all_irqs_0	14.405m	5.439ms	3	3	100.00
		chip_plic_all_irqs_10	15.238m	8.173ms	3	3	100.00
		chip_sw_dma_inline_hashing	7.796m	4.979ms	3	3	100.00
		chip_sw_dma_abort	6.610m	5.587ms	0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	17.711s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	17.368s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	18.595s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	18.587s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	19.244s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	17.255s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	17.412s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	18.421s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	18.044s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	18.916s		0	3	0.00
		chip_sw_entropy_src_smoketest	8.461m	4.859ms	3	3	100.00
		chip_sw_mbx_smoketest	8.604m	5.914ms	3	3	100.00
		TOTAL			2022	2668	75.79

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
72.97	73.86	78.19	63.51	57.14	80.93	67.67	89.50

Failure Buckets

• Job returned non-zero exit code has 455 failures:

  • Test chip_sw_example_manufacturer has 3 failures.

    • 0.chip_sw_example_manufacturer.45328789171053998585154162883456471299134077845899354300719518930136828360402
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

        Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 7.649s, Critical Path: 0.17s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_example_manufacturer.85153197844306999085166535005679812379531239740572495799713981487870245251926
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

        Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 1.251s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test chip_sw_data_integrity_escalation has 6 failures.

    • 0.chip_sw_data_integrity_escalation.43849098967218315881599301530037056832410911124194392880030819881349393914840
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

        Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 162.011s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_data_integrity_escalation.9956491044148507738087740839676936522848713500350902885390994149540690890833
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log

        Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 8.246s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 4 more failures.

  • Test chip_sw_sleep_pin_wake has 3 failures.

    • 0.chip_sw_sleep_pin_wake.61559780621104586200370284670768028282636133554954320485424184271902143481912
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

        Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:sleep_pin_wake_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 156.735s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_sleep_pin_wake.54473946910130180647725978497154792765280075513462135240312387502525132530193
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log

        Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:sleep_pin_wake_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 1.744s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test chip_sw_sleep_pin_retention has 3 failures.

    • 0.chip_sw_sleep_pin_retention.14154351979958557588034449198817964944812668997971647813099478286814111859377
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

        Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:sleep_pin_retention_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 146.154s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_sleep_pin_retention.24204263574274974555293409726590844728663414749380334163274379626321248730529
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log

        Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:sleep_pin_retention_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 8.772s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test chip_sw_uart_tx_rx has 5 failures.

    • 0.chip_sw_uart_tx_rx.84905885413102699563797347513473954788046600712980642888625445064807585949794
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

        [0 / 1] [Prepa] BazelWorkspaceStatusAction stable-status.txt
        Target //sw/device/tests:uart_tx_rx_test_sim_dv failed to build
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:uart_tx_rx_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 125.778s, Critical Path: 0.00s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_uart_tx_rx.33709930026581790467639386670670160921347503831484651409992887703592005438433
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_uart_tx_rx/latest/run.log

        Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)
      
        Use --verbose_failures to see the command lines of failed build steps.
        ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
        Dependency chain:
            //sw/device/tests:uart_tx_rx_test_sim_dv (62e3c7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
        INFO: Elapsed time: 3.210s, Critical Path: 0.01s
        INFO: 1 process: 1 internal.
        ERROR: Build did NOT complete successfully
        make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 3 more failures.

  • ... and 131 more tests.

• Job timed out after * minutes has 37 failures:

  • Test xbar_access_same_device_slow_rsp has 36 failures.

    • 2.xbar_access_same_device_slow_rsp.113203201868449526384232067012895826304984395258951716943187892298125690559114
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_access_same_device_slow_rsp/latest/run.log

        Job timed out after 60 minutes
      

    • 4.xbar_access_same_device_slow_rsp.79282097166602887888676337448154166188568954344952300304321450177678983525784
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_access_same_device_slow_rsp/latest/run.log

        Job timed out after 60 minutes
      

    • ... and 34 more failures.

  • Test xbar_stress_all_with_reset_error has 1 failures.

    • 76.xbar_stress_all_with_reset_error.65521267724397726593799133760936365136718984385787103358107692829092922767803
      Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/76.xbar_stress_all_with_reset_error/latest/run.log

        Job timed out after 60 minutes
      

• UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 27 failures:

  • Test chip_sw_aes_enc_jitter_en has 3 failures.

    • 0.chip_sw_aes_enc_jitter_en.34664366561771432593555831526103428705140557975133726839712562075325355784598
      Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_aes_enc_jitter_en.49305578343218611726127695160178241636592489842239710111373590070355599897393
      Line 382, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_hmac_enc_jitter_en has 3 failures.

    • 0.chip_sw_hmac_enc_jitter_en.77374675489432885899020584086881275986617559214284168267451965644494927234473
      Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_hmac_enc_jitter_en.57782649647275621543997918752096266614304516330212773381407166326687750252599
      Line 423, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log

        UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 3 failures.

    • 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.28396818718263010428889182316109648446172680381013359003342795742439938359416
      Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log

        UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_keymgr_dpe_key_derivation_jitter_en.71620994676589269619102653966022402322115491613907174612843111250240957915776
      Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log

        UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_kmac_mode_kmac_jitter_en has 3 failures.

    • 0.chip_sw_kmac_mode_kmac_jitter_en.51861934744534555696206206694831013195094623435600213468501804915124834729336
      Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log

        UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_kmac_mode_kmac_jitter_en.37144300995694729381226730242335411192436256140227353745239821182915565862971
      Line 412, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log

        UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_aes_enc_jitter_en_reduced_freq has 3 failures.

    • 0.chip_sw_aes_enc_jitter_en_reduced_freq.103558380594675811871456773255879492597296680826006237795500477963898825320997
      Line 381, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log

        UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_aes_enc_jitter_en_reduced_freq.114868770994855788850282287884202424575276968099318795047175808502815069049392
      Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log

        UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
        UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • ... and 4 more tests.

• Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 24 failures:

  • Test chip_tl_errors has 24 failures.

    • 0.chip_tl_errors.66371422910450935710274419500525070385413703079165599555262502331191661293762
      Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

            Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
        UVM_ERROR @ 3245.872936 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
        UVM_INFO @ 3245.872936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.chip_tl_errors.14602254957660214086412636227416473543203859530234071537539879452166106593211
      Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_tl_errors/latest/run.log

            Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
        UVM_ERROR @ 3167.972010 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
        UVM_INFO @ 3167.972010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 22 more failures.

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 12 failures:

  • Test chip_sw_rstmgr_cpu_info has 3 failures.

    • 0.chip_sw_rstmgr_cpu_info.80039724825261998820776151010589040806844694192618215291877355644695915237684
      Line 423, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

        UVM_ERROR @ 20018.482459 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns
      
        UVM_INFO @ 20018.482459 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_rstmgr_cpu_info.29386172221214251364287714323512035322648527341747485285433380224491651687824
      Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

        UVM_ERROR @ 20018.509438 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns
      
        UVM_INFO @ 20018.509438 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_aon_timer_irq has 3 failures.

    • 0.chip_sw_aon_timer_irq.70945521473404855248413612127265517257783199218557050116815754499729381356277
      Line 432, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

        UVM_ERROR @ 18018.398153 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
      
        UVM_INFO @ 18018.398153 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_aon_timer_irq.76530827559061420194769131236477684612614433062978531184431308275298751569675
      Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log

        UVM_ERROR @ 18026.817953 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
      
        UVM_INFO @ 18026.817953 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 5 failures.

    • 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.114072078441778830304290169754307588814618033747435561814882969336281772633443
      Line 421, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

        UVM_ERROR @ 18018.561847 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
      
        UVM_INFO @ 18018.561847 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.16650336483345763963744728431655456825869453701537575646872870752874257389559
      Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

        UVM_ERROR @ 18018.640359 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
      
        UVM_INFO @ 18018.640359 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

  • Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

    • 2.chip_sw_clkmgr_off_otbn_trans.9649016886226253248239757098655805599998260545443391555592904978819893523801
      Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_clkmgr_off_otbn_trans/latest/run.log

        UVM_ERROR @ 12026.818710 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12026.818710 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 11 failures:

  • Test chip_sw_clkmgr_off_aes_trans has 3 failures.

    • 0.chip_sw_clkmgr_off_aes_trans.20734724022368271771674740318332760498542350519044745521764391668620506736848
      Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

        UVM_ERROR @ 12026.886529 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12026.886529 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_clkmgr_off_aes_trans.112870222402661302074097632835171885732098522809220997959082400672365354137194
      Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log

        UVM_ERROR @ 12026.771162 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12026.771162 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_clkmgr_off_hmac_trans has 3 failures.

    • 0.chip_sw_clkmgr_off_hmac_trans.9463022108230712768357434980454800421529208036750770372524377622207949546828
      Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

        UVM_ERROR @ 12026.859578 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12026.859578 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_clkmgr_off_hmac_trans.97028197370233630158100952442209498875640686395288512804972499770321253850802
      Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log

        UVM_ERROR @ 12018.391185 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12018.391185 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_clkmgr_off_kmac_trans has 3 failures.

    • 0.chip_sw_clkmgr_off_kmac_trans.94436974699511537158354654915955697201693504771693652815000528189334685128026
      Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

        UVM_ERROR @ 12018.564251 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12018.564251 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_clkmgr_off_kmac_trans.101052973156452731131417343832883108199562553738877309072352827651243483302174
      Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log

        UVM_ERROR @ 12026.903686 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12026.903686 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_clkmgr_off_otbn_trans has 2 failures.

    • 0.chip_sw_clkmgr_off_otbn_trans.216740277526557959513376462259398426583478809331588420198617141742675453187
      Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

        UVM_ERROR @ 12026.934745 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12026.934745 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_clkmgr_off_otbn_trans.46083534857375604451029660167247716790802042673343297810077974626454931496057
      Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_clkmgr_off_otbn_trans/latest/run.log

        UVM_ERROR @ 12026.810511 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12026.810511 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:

  • Test chip_padctrl_attributes has 10 failures.

    • 0.chip_padctrl_attributes.83847270470828836298847187650550895880114461144985647704271798545403669662748
      Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.
      

    • 1.chip_padctrl_attributes.111720862885429110787460298046575461681397534892934049638688218183693957838057
      Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.
      

    • ... and 8 more failures.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:

  • Test chip_csr_bit_bash has 3 failures.

    • 0.chip_csr_bit_bash.89557491092899902055155951115541358728908729975498840809275600358843781290799
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_csr_bit_bash.76236266377892891346359688500542848098473893707775394529901578992359375153458
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_csr_aliasing has 3 failures.

    • 0.chip_csr_aliasing.53078991175928958500178207129280251120549588901067227081636182927513477316184
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_csr_aliasing.9570349049877674768772611738022927394712484723628116694768582453544038709289
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_same_csr_outstanding has 3 failures.

    • 0.chip_same_csr_outstanding.6695705546737927581798235817737376497004523767006402632827059440406530924239
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_same_csr_outstanding.46790737254414293779846916992470694053756803970992010858458373287559939262166
      Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log

        UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
        UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 6 failures:

  • Test chip_sw_keymgr_dpe_key_derivation has 3 failures.

    • 0.chip_sw_keymgr_dpe_key_derivation.22370575059572637807207883593371384777613677459342899941611740206672280550137
      Line 416, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

        UVM_ERROR @ 6898.330636 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (6552230994799355219796613541485169199019152612627447910335187551895217923363649403525045340458818233826206369756795646445257360297831342555557180263980124 [0x7d1aa351aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3fb4c13a07f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 6898.330636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_keymgr_dpe_key_derivation.108214359723275850272538981270814490772937900304900039422268404722646362035658
      Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log

        UVM_ERROR @ 6266.876640 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (6424980070193401120738537057033501460502483785128653349484291787623841105782687792677693653201127758848658036179594587110183677021982173207584453213641820 [0x7aaca5fdaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3fcfa150c7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 6266.876640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_sw_keymgr_dpe_key_derivation_prod has 3 failures.

    • 0.chip_sw_keymgr_dpe_key_derivation_prod.223276216652552620154904613396693884362045164788562078711168140232453550724
      Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

        UVM_ERROR @ 9368.982354 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (2677167445406330510258897012294210840050370667785876931576328414564191473051872451988341728063843940079103876214688220236842460643494820117551394767330396 [0x331db8cdaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3b54b083c7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 9368.982354 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_keymgr_dpe_key_derivation_prod.60035963510972447723587121667246904084399345761762699458313396446024134143508
      Line 449, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

        UVM_ERROR @ 7764.289732 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (1807857744706405969821059802984897149168306905623209763898142821780230410748570161335838306136622041449824277097752270219151275477306818114655992397782108 [0x22849fe4aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3a4d22f157f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
        UVM_INFO @ 7764.289732 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:

  • Test chip_jtag_csr_rw has 3 failures.

    • 0.chip_jtag_csr_rw.46591695321023016695626647285625952789308704186342978979167851558666455604325
      Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

        UVM_ERROR @ 4087.649731 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'h2f26c1fc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1f  a_opcode: 'h1  a_user: 'h248cb  d_param: 'h0  d_source: 'h1f  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 4087.649731 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_jtag_csr_rw.109270844083248163259188677702632921459878777006601591838641782726081766180435
      Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log

        UVM_ERROR @ 3883.653903 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'h43ad50ca  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3e  a_opcode: 'h1  a_user: 'h2489f  d_param: 'h0  d_source: 'h3e  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 3883.653903 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test chip_jtag_mem_access has 3 failures.

    • 0.chip_jtag_mem_access.83763140588195694561802399060366892161736687655037334298459699682499603271287
      Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

        UVM_ERROR @ 5457.671694 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'hde6293a0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h16  a_opcode: 'h1  a_user: 'h248f1  d_param: 'h0  d_source: 'h16  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 5457.671694 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_jtag_mem_access.75026535280112827111840715625132752306600139939992592085198516393194579260327
      Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log

        UVM_ERROR @ 3220.176855 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47283) { a_addr: 'h30480000  a_data: 'ha85cc7a4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h9  a_opcode: 'h0  a_user: 'h26965  d_param: 'h0  d_source: 'h9  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 3220.176855 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault has 5 failures:

  • Test chip_sw_all_escalation_resets has 5 failures.

    • 13.chip_sw_all_escalation_resets.21905230004017306837402839818893430671079029571996050463407434402544158720703
      Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 4690.608720 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
        UVM_INFO @ 4690.608720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 21.chip_sw_all_escalation_resets.88150486082033857466700111782042959401801935675768424799871969945816115286933
      Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 5997.013932 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
        UVM_INFO @ 5997.013932 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 3 failures:

  • Test chip_sw_example_rom has 3 failures.

    • 0.chip_sw_example_rom.94039607250871480343343211069426315591299820518845431354156977337117476374530
      Line 366, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

        UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
        UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_example_rom.46458303161467841400334606481669257763615076547423528533987755101705802801471
      Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log

        UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
        UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 3 failures:

  • Test chip_sw_all_escalation_resets has 3 failures.

    • 0.chip_sw_all_escalation_resets.36604943096576930769234409713318055144031915537632069498863725712039302584605
      Line 1415, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log

        UVM_FATAL @  10.220001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
        UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 66.chip_sw_all_escalation_resets.18657343921829014020789293883442290874239108133096504664999577936813910132943
      Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/66.chip_sw_all_escalation_resets/latest/run.log

        UVM_FATAL @  10.400001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
        UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:

  • Test chip_sw_spi_device_pass_through_collision has 3 failures.

    • 0.chip_sw_spi_device_pass_through_collision.102812587918925984928452139382137638140523757918331662460727757807579086265253
      Line 431, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log

        UVM_ERROR @ 5543.635216 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
        UVM_INFO @ 5543.635216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_spi_device_pass_through_collision.90398387772952567697391558750351062291311967014905206286060147771109534842837
      Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log

        UVM_ERROR @ 3907.436352 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
        UVM_INFO @ 3907.436352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 3 failures:

  • Test chip_sw_rstmgr_alert_info has 3 failures.

    • 0.chip_sw_rstmgr_alert_info.78427992793958397985582171578902150118688161198615908568998971664534577692312
      Line 661, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

        UVM_ERROR @ 6572.640425 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
        UVM_INFO @ 6572.640425 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_rstmgr_alert_info.9797204782300465472523640164238609795179939188392345135271036763822150954073
      Line 626, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log

        UVM_ERROR @ 9250.785488 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
        UVM_INFO @ 9250.785488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 3 failures:

  • Test chip_sw_soc_proxy_external_alerts has 3 failures.

    • 0.chip_sw_soc_proxy_external_alerts.104816342220093952349481313952908646457125306444396077314446593653783830239255
      Line 425, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log

        UVM_ERROR @ 5045.886428 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
        UVM_INFO @ 5045.886428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_soc_proxy_external_alerts.73834541375034908675260951563481238986578287554071032492124059192142247769680
      Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_alerts/latest/run.log

        UVM_ERROR @ 3818.096400 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
        UVM_INFO @ 3818.096400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 3 failures:

  • Test chip_sw_soc_proxy_external_wakeup has 3 failures.

    • 0.chip_sw_soc_proxy_external_wakeup.97638018309729296160862415635986951102358354602801008257429492090284811420346
      Line 429, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log

        UVM_ERROR @ 3916.483127 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
        UVM_INFO @ 3916.483127 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_soc_proxy_external_wakeup.27330361220486299650285355090461281712743055450914919325322921481344556622625
      Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log

        UVM_ERROR @ 5429.884942 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
        UVM_INFO @ 5429.884942 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 3 failures:

  • Test chip_sw_aon_timer_wdog_bite_reset has 3 failures.

    • 0.chip_sw_aon_timer_wdog_bite_reset.100124339993296370887249725192743666534916994325715431882062820427318247902282
      Line 416, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log

        UVM_ERROR @ 3837.165032 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
        UVM_INFO @ 3837.165032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_aon_timer_wdog_bite_reset.102601977301700360467807464489818998697546931628683926253347586544073086565793
      Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log

        UVM_ERROR @ 3747.386155 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
        UVM_INFO @ 3747.386155 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:

  • Test chip_sw_rv_core_ibex_nmi_irq has 3 failures.

    • 0.chip_sw_rv_core_ibex_nmi_irq.5939449191322438038906946577241258679970096281505979484137019105858259554873
      Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log

        UVM_ERROR @ 5864.215245 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
        UVM_INFO @ 5864.215245 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_rv_core_ibex_nmi_irq.57345754127013468807438332631779878141909607249438221667375331329813120890521
      Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log

        UVM_ERROR @ 4990.823352 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
        UVM_INFO @ 4990.823352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:

  • Test chip_sw_kmac_app_rom has 3 failures.

    • 0.chip_sw_kmac_app_rom.67944369695204843885391937032286445238536333845634259113702982879126004166938
      Line 400, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log

        UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
        UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_kmac_app_rom.65739859430013043896102366396736410407617546716930921623048407475489086373016
      Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log

        UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
        UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 3 failures:

  • Test chip_rv_dm_ndm_reset_req has 3 failures.

    • 0.chip_rv_dm_ndm_reset_req.94178209353434470510568041321926698707162277084749994539830603902498813548744
      Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log

        UVM_FATAL @ 14228.600404 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
        UVM_INFO @ 14228.600404 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_rv_dm_ndm_reset_req.48182101203851300932716534902422666077698108719563607156801620459778003043349
      Line 376, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest/run.log

        UVM_FATAL @ 15998.904954 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
        UVM_INFO @ 15998.904954 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 3 failures:

  • Test chip_sw_dma_abort has 3 failures.

    • 0.chip_sw_dma_abort.95862858762455407067974850012651452723391335150767432771126476223396702787437
      Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

        UVM_FATAL @ 5941.245480 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
        UVM_INFO @ 5941.245480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.chip_sw_dma_abort.85373825303128892794030268640566109026525052569938054737644951588822225384984
      Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log

        UVM_FATAL @ 4306.619070 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
        UVM_INFO @ 4306.619070 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

  • Test chip_sw_all_escalation_resets has 3 failures.

    • 9.chip_sw_all_escalation_resets.77451934582486900205435793172992468676503381676959637408512553223933294063111
      Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 12026.879718 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12026.879718 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 29.chip_sw_all_escalation_resets.11193532492300157661201649937369900662968748249326287470256060055537975876869
      Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/29.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 12018.608378 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12018.608378 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37600) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_tl_errors has 1 failures.

    • 1.chip_tl_errors.50913541821660861937732325045927600112482256643036210687831754841727186135594
      Line 231, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log

        UVM_ERROR @ 3336.998131 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37600) { a_addr: 'h4046c  a_data: 'hf594e86  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h18  a_opcode: 'h4  a_user: 'h19ab5  d_param: 'h0  d_source: 'h18  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 3336.998131 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:

  • Test chip_rv_dm_lc_disabled has 1 failures.

    • 1.chip_rv_dm_lc_disabled.56545895299835109716297779321550319012407924898575533400815149926899832948399
      Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log

        UVM_ERROR @ 9535.971804 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x40734 read out mismatch
        UVM_INFO @ 9535.971804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36932) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_tl_errors has 1 failures.

    • 7.chip_tl_errors.28621956593654493008608781177007489524932133201012461654162625714532179450708
      Line 231, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_tl_errors/latest/run.log

        UVM_ERROR @ 3952.756368 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36932) { a_addr: 'h4042c  a_data: 'h90c4d8dd  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h11  a_opcode: 'h4  a_user: 'h1b256  d_param: 'h0  d_source: 'h11  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 3952.756368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37364) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_tl_errors has 1 failures.

    • 17.chip_tl_errors.28463939003498896310918056969301078184943062991317113158584623915290307696355
      Line 231, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/17.chip_tl_errors/latest/run.log

        UVM_ERROR @ 3555.214632 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37364) { a_addr: 'h4035c  a_data: 'hc0907a75  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h34  a_opcode: 'h4  a_user: 'h1b9fa  d_param: 'h0  d_source: 'h34  d_data: 'h100073  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd04  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 3555.214632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@49542) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_tl_errors has 1 failures.

    • 21.chip_tl_errors.76771731898424583636530513098895526279710747704012156234357466151792484474526
      Line 231, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/21.chip_tl_errors/latest/run.log

        UVM_ERROR @ 3587.258500 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@49542) { a_addr: 'h40624  a_data: 'hd6b3b17f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1f  a_opcode: 'h4  a_user: 'h1ade6  d_param: 'h0  d_source: 'h1f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 3587.258500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38834) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

  • Test chip_tl_errors has 1 failures.

    • 27.chip_tl_errors.13631589407445341287911577205218308061051240545408251207384975492307768454199
      Line 231, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/27.chip_tl_errors/latest/run.log

        UVM_ERROR @ 3397.485600 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38834) { a_addr: 'h406c0  a_data: 'h65a55ee9  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h30  a_opcode: 'h4  a_user: 'h1a184  d_param: 'h0  d_source: 'h30  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
        , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
        UVM_INFO @ 3397.485600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:

  • Test chip_sw_all_escalation_resets has 1 failures.

    • 65.chip_sw_all_escalation_resets.71230605215472135353945140514999938365521397689158578177884218814976743402770
      Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/65.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 5009.397476 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
        UVM_INFO @ 5009.397476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:

  • Test chip_sw_all_escalation_resets has 1 failures.

    • 79.chip_sw_all_escalation_resets.94655516684892558828804056780856115306442162618625170538146380849944003026109
      Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/79.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 12018.408290 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
      
        UVM_INFO @ 12018.408290 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---