AES/MASKED Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	127.295us	1	1	100.00
V1	smoke	aes_smoke	33.000s	1.519ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	128.638us	5	5	100.00
V1	csr_rw	aes_csr_rw	2.000s	64.268us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	2.361ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	557.894us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	142.781us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	64.268us	20	20	100.00
		aes_csr_aliasing	3.000s	557.894us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	33.000s	1.519ms	50	50	100.00
		aes_config_error	7.000s	257.353us	50	50	100.00
		aes_stress	16.000s	814.826us	50	50	100.00
V2	key_length	aes_smoke	33.000s	1.519ms	50	50	100.00
		aes_config_error	7.000s	257.353us	50	50	100.00
		aes_stress	16.000s	814.826us	50	50	100.00
V2	back2back	aes_stress	16.000s	814.826us	50	50	100.00
		aes_b2b	26.000s	541.437us	50	50	100.00
V2	backpressure	aes_stress	16.000s	814.826us	50	50	100.00
V2	multi_message	aes_smoke	33.000s	1.519ms	50	50	100.00
		aes_config_error	7.000s	257.353us	50	50	100.00
		aes_stress	16.000s	814.826us	50	50	100.00
		aes_alert_reset	28.000s	7.197ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	3.000s	71.700us	50	50	100.00
		aes_config_error	7.000s	257.353us	50	50	100.00
		aes_alert_reset	28.000s	7.197ms	50	50	100.00
V2	trigger_clear_test	aes_clear	23.000s	1.715ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	904.272us	1	1	100.00
V2	reset_recovery	aes_alert_reset	28.000s	7.197ms	50	50	100.00
V2	stress	aes_stress	16.000s	814.826us	50	50	100.00
V2	sideload	aes_stress	16.000s	814.826us	50	50	100.00
		aes_sideload	6.000s	115.768us	50	50	100.00
V2	deinitialization	aes_deinit	24.000s	2.552ms	50	50	100.00
V2	stress_all	aes_stress_all	46.000s	910.685us	9	10	90.00
V2	alert_test	aes_alert_test	3.000s	111.029us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	3.000s	170.644us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	3.000s	170.644us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	128.638us	5	5	100.00
		aes_csr_rw	2.000s	64.268us	20	20	100.00
		aes_csr_aliasing	3.000s	557.894us	5	5	100.00
		aes_same_csr_outstanding	3.000s	73.017us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	128.638us	5	5	100.00
		aes_csr_rw	2.000s	64.268us	20	20	100.00
		aes_csr_aliasing	3.000s	557.894us	5	5	100.00
		aes_same_csr_outstanding	3.000s	73.017us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	17.000s	3.014ms	50	50	100.00
V2S	fault_inject	aes_fi	35.000s	3.820ms	50	50	100.00
		aes_control_fi	55.000s	10.004ms	288	300	96.00
		aes_cipher_fi	36.000s	10.021ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	130.784us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	130.784us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	130.784us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	130.784us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	147.964us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	981.577us	5	5	100.00
		aes_tl_intg_err	4.000s	413.414us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	413.414us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	28.000s	7.197ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	130.784us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	33.000s	1.519ms	50	50	100.00
		aes_stress	16.000s	814.826us	50	50	100.00
		aes_alert_reset	28.000s	7.197ms	50	50	100.00
		aes_core_fi	1.050m	10.003ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	130.784us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	125.349us	50	50	100.00
		aes_stress	16.000s	814.826us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	16.000s	814.826us	50	50	100.00
		aes_sideload	6.000s	115.768us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	125.349us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	125.349us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	125.349us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	125.349us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	125.349us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	16.000s	814.826us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	16.000s	814.826us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	35.000s	3.820ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	35.000s	3.820ms	50	50	100.00
		aes_control_fi	55.000s	10.004ms	288	300	96.00
		aes_cipher_fi	36.000s	10.021ms	336	350	96.00
		aes_ctr_fi	3.000s	83.870us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	35.000s	3.820ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	35.000s	3.820ms	50	50	100.00
		aes_control_fi	55.000s	10.004ms	288	300	96.00
		aes_cipher_fi	36.000s	10.021ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	36.000s	10.021ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	35.000s	3.820ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	35.000s	3.820ms	50	50	100.00
		aes_control_fi	55.000s	10.004ms	288	300	96.00
		aes_ctr_fi	3.000s	83.870us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	35.000s	3.820ms	50	50	100.00
		aes_control_fi	55.000s	10.004ms	288	300	96.00
		aes_cipher_fi	36.000s	10.021ms	336	350	96.00
		aes_ctr_fi	3.000s	83.870us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	28.000s	7.197ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	35.000s	3.820ms	50	50	100.00
		aes_control_fi	55.000s	10.004ms	288	300	96.00
		aes_cipher_fi	36.000s	10.021ms	336	350	96.00
		aes_ctr_fi	3.000s	83.870us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	35.000s	3.820ms	50	50	100.00
		aes_control_fi	55.000s	10.004ms	288	300	96.00
		aes_cipher_fi	36.000s	10.021ms	336	350	96.00
		aes_ctr_fi	3.000s	83.870us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	35.000s	3.820ms	50	50	100.00
		aes_control_fi	55.000s	10.004ms	288	300	96.00
		aes_ctr_fi	3.000s	83.870us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	35.000s	3.820ms	50	50	100.00
		aes_control_fi	55.000s	10.004ms	288	300	96.00
		aes_cipher_fi	36.000s	10.021ms	336	350	96.00
V2S		TOTAL			957	985	97.16
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	32.000s	1.223ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1563	1602	97.57

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.33	98.59	96.43	99.43	95.30	98.07	97.78	98.36	98.79

Failure Buckets

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 22.aes_cipher_fi.81615364168785579211860868443830204988566420153268713511194267867070979093361
    Line 134, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10017960343 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017960343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 57.aes_cipher_fi.94018258784018470666056998600289389885457249910848549946283617858846918264753
    Line 137, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/57.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10029536503 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10029536503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.
Job timed out after * minutes has 9 failures:
- Test aes_control_fi has 7 failures.
  - 25.aes_control_fi.32154801479860280792595326374283026019686889667155392589238425105103288155462
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 41.aes_control_fi.110321215511685006325989845457766525672739286945900910941998144460561500867049
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/41.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 5 more failures.
- Test aes_cipher_fi has 2 failures.
  - 131.aes_cipher_fi.82582888425951820601463463854992342276518623669986247843584861528957442888594
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/131.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 155.aes_cipher_fi.67321910858651044805364773890060467101330925992391647224851974136274666014293
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/155.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.37932780742197822416012573590303191088381042873220796196538385679467571090016
Line 792, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1900557685 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1900557685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.22683367093316740309234898921493193811261002028835849039737959589963424559925
Line 1303, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1222797276 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1222797276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 23.aes_control_fi.79243611093559216387026209531506958978642299289879784951808692745654188604732
    Line 144, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004618868 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004618868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 28.aes_control_fi.113826851277701736125217541673241931329291461373913574884402093077123156222999
    Line 139, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/28.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011235083 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011235083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.78997277294848913846221419360195868761250306532934661577483993944785735395791
    Line 258, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4223991591 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4223991591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_stress_all_with_rand_reset.20069213486963811683980540331436811042090735538410244719410625576244519135483
    Line 140, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 221094683 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 221094683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.23303903265078896408981167184922293915158731212521707390947861805356749806261
    Line 486, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 408501624 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 408501624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

7.aes_stress_all.9757407424784697566973180865266876517846386311115040306043240053037509222724
Line 20549, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/7.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 203752655 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 203712655 PS)
  UVM_ERROR @ 203752655 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 203752655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 18.aes_core_fi.115120257427678222536008656387644202413438628401711024861885600799997811432868
    Line 146, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002725133 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002725133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 26.aes_core_fi.76478451858091029970690230194401567799273981124821698103889707204516557227946
    Line 132, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/26.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013578226 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013578226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```