AES/UNMASKED Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	54.170us	1	1	100.00
V1	smoke	aes_smoke	3.000s	64.616us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	55.270us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	61.846us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	339.206us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	114.389us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	69.484us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	61.846us	20	20	100.00
		aes_csr_aliasing	6.000s	114.389us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	3.000s	64.616us	50	50	100.00
		aes_config_error	6.000s	439.509us	50	50	100.00
		aes_stress	4.000s	374.260us	50	50	100.00
V2	key_length	aes_smoke	3.000s	64.616us	50	50	100.00
		aes_config_error	6.000s	439.509us	50	50	100.00
		aes_stress	4.000s	374.260us	50	50	100.00
V2	back2back	aes_stress	4.000s	374.260us	50	50	100.00
		aes_b2b	8.000s	382.644us	50	50	100.00
V2	backpressure	aes_stress	4.000s	374.260us	50	50	100.00
V2	multi_message	aes_smoke	3.000s	64.616us	50	50	100.00
		aes_config_error	6.000s	439.509us	50	50	100.00
		aes_stress	4.000s	374.260us	50	50	100.00
		aes_alert_reset	4.000s	296.825us	50	50	100.00
V2	failure_test	aes_man_cfg_err	3.000s	85.549us	50	50	100.00
		aes_config_error	6.000s	439.509us	50	50	100.00
		aes_alert_reset	4.000s	296.825us	50	50	100.00
V2	trigger_clear_test	aes_clear	4.000s	962.624us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	5.000s	664.238us	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.000s	296.825us	50	50	100.00
V2	stress	aes_stress	4.000s	374.260us	50	50	100.00
V2	sideload	aes_stress	4.000s	374.260us	50	50	100.00
		aes_sideload	3.000s	231.081us	50	50	100.00
V2	deinitialization	aes_deinit	4.000s	179.062us	50	50	100.00
V2	stress_all	aes_stress_all	19.000s	3.097ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	115.338us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	366.905us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	366.905us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	55.270us	5	5	100.00
		aes_csr_rw	6.000s	61.846us	20	20	100.00
		aes_csr_aliasing	6.000s	114.389us	5	5	100.00
		aes_same_csr_outstanding	6.000s	101.769us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	55.270us	5	5	100.00
		aes_csr_rw	6.000s	61.846us	20	20	100.00
		aes_csr_aliasing	6.000s	114.389us	5	5	100.00
		aes_same_csr_outstanding	6.000s	101.769us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	4.000s	244.778us	50	50	100.00
V2S	fault_inject	aes_fi	4.000s	179.085us	49	50	98.00
		aes_control_fi	58.000s	200.000ms	285	300	95.00
		aes_cipher_fi	54.000s	10.008ms	328	350	93.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	93.169us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	93.169us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	93.169us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	93.169us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	109.452us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	853.737us	5	5	100.00
		aes_tl_intg_err	7.000s	127.616us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	127.616us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	296.825us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	93.169us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	3.000s	64.616us	50	50	100.00
		aes_stress	4.000s	374.260us	50	50	100.00
		aes_alert_reset	4.000s	296.825us	50	50	100.00
		aes_core_fi	29.000s	10.011ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	93.169us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	95.732us	50	50	100.00
		aes_stress	4.000s	374.260us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	374.260us	50	50	100.00
		aes_sideload	3.000s	231.081us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	95.732us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	95.732us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	95.732us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	95.732us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	95.732us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	374.260us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	374.260us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	4.000s	179.085us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	4.000s	179.085us	49	50	98.00
		aes_control_fi	58.000s	200.000ms	285	300	95.00
		aes_cipher_fi	54.000s	10.008ms	328	350	93.71
		aes_ctr_fi	3.000s	63.747us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	4.000s	179.085us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	4.000s	179.085us	49	50	98.00
		aes_control_fi	58.000s	200.000ms	285	300	95.00
		aes_cipher_fi	54.000s	10.008ms	328	350	93.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	54.000s	10.008ms	328	350	93.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	4.000s	179.085us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	4.000s	179.085us	49	50	98.00
		aes_control_fi	58.000s	200.000ms	285	300	95.00
		aes_ctr_fi	3.000s	63.747us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	4.000s	179.085us	49	50	98.00
		aes_control_fi	58.000s	200.000ms	285	300	95.00
		aes_cipher_fi	54.000s	10.008ms	328	350	93.71
		aes_ctr_fi	3.000s	63.747us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	296.825us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	4.000s	179.085us	49	50	98.00
		aes_control_fi	58.000s	200.000ms	285	300	95.00
		aes_cipher_fi	54.000s	10.008ms	328	350	93.71
		aes_ctr_fi	3.000s	63.747us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	4.000s	179.085us	49	50	98.00
		aes_control_fi	58.000s	200.000ms	285	300	95.00
		aes_cipher_fi	54.000s	10.008ms	328	350	93.71
		aes_ctr_fi	3.000s	63.747us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	4.000s	179.085us	49	50	98.00
		aes_control_fi	58.000s	200.000ms	285	300	95.00
		aes_ctr_fi	3.000s	63.747us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	4.000s	179.085us	49	50	98.00
		aes_control_fi	58.000s	200.000ms	285	300	95.00
		aes_cipher_fi	54.000s	10.008ms	328	350	93.71
V2S		TOTAL			943	985	95.74
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	16.000s	7.327ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1550	1602	96.75

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.21	97.64	94.67	98.76	93.26	97.99	91.11	98.08	97.99

Failure Buckets

Job timed out after * minutes has 23 failures:
- Test aes_control_fi has 10 failures.
  - 1.aes_control_fi.52154035636150284184577203691233815172388095795446816739285520957735992578676
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 46.aes_control_fi.16689718502354890513438205253924128102205294715670017816147681135508338123308
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/46.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 8 more failures.
- Test aes_cipher_fi has 13 failures.
  - 21.aes_cipher_fi.80217924299654491539510855964959704084159484275203237032290413264888216949953
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/21.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 54.aes_cipher_fi.84108509792430575883812402465798748393417196198440981695880325527306014243565
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/54.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 41.aes_cipher_fi.77069387360189685295625326504122673762771593191525269863301189343238886639108
    Line 141, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/41.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10016454878 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016454878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 47.aes_cipher_fi.107057532631939278039808629876680690697337413893192838767170709565255933262422
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/47.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007988268 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007988268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.55050146125532088643803417962217891081327953238717175848750959979022500357056
Line 828, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1169712184 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1169712184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.111572524825233710868752829612958147835996353767868644539507251780542894976395
Line 415, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 376434832 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 376434832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 88.aes_control_fi.115602834089044686110110829277850415387058977058832663808412091795087279070060
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/88.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002808678 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002808678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 90.aes_control_fi.24156766966065005943269459591217513955671872001812838082718623159375288417157
    Line 142, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/90.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002980345 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002980345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 7.aes_stress_all_with_rand_reset.79988182124128286464212040014747967561373984135378944535865506082310057930847
    Line 211, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  87458312 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  87458312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.aes_stress_all_with_rand_reset.83278253168809525504043796917136217936488248274259196127027714231219827474118
    Line 1168, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 404295057 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 404295057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 25.aes_core_fi.83556334484717198832025317159685848081771501393145109473287517970623206525044
    Line 133, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/25.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011408607 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011408607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 32.aes_core_fi.99902576501074599403061715995505192279784844193121303285858459983502047539822
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/32.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10057442578 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10057442578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 62.aes_core_fi.91959044618760461839201680996247679246758738078646880619855860736060752854205
    Line 153, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/62.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007642914 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007642914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 64.aes_core_fi.35390993333783359085638853062189328536299989513493878607557336415655926311692
    Line 145, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/64.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007731612 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007731612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 8.aes_fi.28135895528411132229262453131967958573171458732882964253801181723370770986197
    Line 8018, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/8.aes_fi/latest/run.log
```
  UVM_FATAL @  73062359 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  73062359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 243.aes_control_fi.90549874314379652355509732429833234534589157567491678190580884886632969473731
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/243.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```