AON_TIMER Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.130s	477.323us	5	5	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.930s	1.131ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.880s	527.593us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	22.790s	10.927ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.740s	643.779us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.630s	366.302us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.880s	527.593us	20	20	100.00
		aon_timer_csr_aliasing	1.740s	643.779us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.110s	434.443us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.210s	480.491us	5	5	100.00
V1		TOTAL			70	70	100.00
V2	prescaler	aon_timer_prescaler	1.358m	43.378ms	15	15	100.00
V2	jump	aon_timer_jump	1.740s	747.723us	5	5	100.00
V2	stress_all	aon_timer_stress_all	1.284m	168.689ms	15	15	100.00
V2	alert_test	aon_timer_alert_test	2.030s	507.474us	50	50	100.00
V2	intr_test	aon_timer_intr_test	1.630s	438.815us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.430s	642.514us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.430s	642.514us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.930s	1.131ms	5	5	100.00
		aon_timer_csr_rw	1.880s	527.593us	20	20	100.00
		aon_timer_csr_aliasing	1.740s	643.779us	5	5	100.00
		aon_timer_same_csr_outstanding	5.450s	2.560ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.930s	1.131ms	5	5	100.00
		aon_timer_csr_rw	1.880s	527.593us	20	20	100.00
		aon_timer_csr_aliasing	1.740s	643.779us	5	5	100.00
		aon_timer_same_csr_outstanding	5.450s	2.560ms	20	20	100.00
V2		TOTAL			175	175	100.00
V2S	tl_intg_err	aon_timer_sec_cm	13.970s	7.573ms	5	5	100.00
		aon_timer_tl_intg_err	13.380s	8.758ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.380s	8.758ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	max_threshold	aon_timer_smoke_max_thold	2.230s	599.565us	5	5	100.00
V3	min_threshold	aon_timer_smoke_min_thold	2.220s	641.030us	5	5	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	14.090s	3.655ms	5	5	100.00
V3	custom_intr	aon_timer_custom_intr	2.290s	511.702us	10	10	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	17.040s	3.997ms	5	5	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	58.690s	22.461ms	15	15	100.00
V3		TOTAL			45	45	100.00
		TOTAL			315	315	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.89	99.09	99.05	100.00	--	98.56	96.67	100.00