CSRNG Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	7.000s	272.510us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	33.590us	5	5	100.00
V1	csr_rw	csrng_csr_rw	3.000s	200.563us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	52.000s	4.073ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	4.000s	189.261us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	310.366us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	3.000s	200.563us	20	20	100.00
		csrng_csr_aliasing	4.000s	189.261us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	17.000s	825.013us	198	200	99.00
V2	alerts	csrng_alert	53.000s	5.169ms	500	500	100.00
V2	err	csrng_err	4.000s	77.049us	494	500	98.80
V2	cmds	csrng_cmds	17.133m	101.970ms	50	50	100.00
V2	life cycle	csrng_cmds	17.133m	101.970ms	50	50	100.00
V2	stress_all	csrng_stress_all	33.950m	174.455ms	45	50	90.00
V2	intr_test	csrng_intr_test	4.000s	157.754us	50	50	100.00
V2	alert_test	csrng_alert_test	7.000s	115.561us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	20.000s	1.843ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	20.000s	1.843ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	33.590us	5	5	100.00
		csrng_csr_rw	3.000s	200.563us	20	20	100.00
		csrng_csr_aliasing	4.000s	189.261us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	563.654us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	33.590us	5	5	100.00
		csrng_csr_rw	3.000s	200.563us	20	20	100.00
		csrng_csr_aliasing	4.000s	189.261us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	563.654us	20	20	100.00
V2		TOTAL			1427	1440	99.10
V2S	tl_intg_err	csrng_sec_cm	9.000s	385.783us	5	5	100.00
		csrng_tl_intg_err	11.000s	427.059us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	84.770us	50	50	100.00
		csrng_csr_rw	3.000s	200.563us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	53.000s	5.169ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	33.950m	174.455ms	45	50	90.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	17.000s	825.013us	198	200	99.00
		csrng_err	4.000s	77.049us	494	500	98.80
		csrng_sec_cm	9.000s	385.783us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	17.000s	825.013us	198	200	99.00
		csrng_err	4.000s	77.049us	494	500	98.80
		csrng_sec_cm	9.000s	385.783us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	17.000s	825.013us	198	200	99.00
		csrng_err	4.000s	77.049us	494	500	98.80
		csrng_sec_cm	9.000s	385.783us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	17.000s	825.013us	198	200	99.00
		csrng_err	4.000s	77.049us	494	500	98.80
		csrng_sec_cm	9.000s	385.783us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	17.000s	825.013us	198	200	99.00
		csrng_err	4.000s	77.049us	494	500	98.80
		csrng_sec_cm	9.000s	385.783us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	17.000s	825.013us	198	200	99.00
		csrng_err	4.000s	77.049us	494	500	98.80
		csrng_sec_cm	9.000s	385.783us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	17.000s	825.013us	198	200	99.00
		csrng_err	4.000s	77.049us	494	500	98.80
		csrng_sec_cm	9.000s	385.783us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	53.000s	5.169ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	17.000s	825.013us	198	200	99.00
		csrng_err	4.000s	77.049us	494	500	98.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	33.950m	174.455ms	45	50	90.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	53.000s	5.169ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	11.000s	427.059us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	17.000s	825.013us	198	200	99.00
		csrng_err	4.000s	77.049us	494	500	98.80
		csrng_sec_cm	9.000s	385.783us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	17.000s	825.013us	198	200	99.00
		csrng_err	4.000s	77.049us	494	500	98.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	17.000s	825.013us	198	200	99.00
		csrng_err	4.000s	77.049us	494	500	98.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	17.000s	825.013us	198	200	99.00
		csrng_err	4.000s	77.049us	494	500	98.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	17.000s	825.013us	198	200	99.00
		csrng_err	4.000s	77.049us	494	500	98.80
		csrng_sec_cm	9.000s	385.783us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	17.000s	825.013us	198	200	99.00
		csrng_err	4.000s	77.049us	494	500	98.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	8.767m	29.318ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1617	1630	99.20

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.68	98.58	96.50	100.00	97.27	92.08	100.00	95.61	90.46

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed has 7 failures:

  • Test csrng_intr has 1 failures.

    • 40.csrng_intr.96127928761695387794185958626439965614318934137066792637923213704147533580157
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/40.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 303310608 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @ 303310608 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @ 303310608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test csrng_err has 6 failures.

    • 54.csrng_err.74361541798345497980759779087825593177362005345976964098641867523603480643395
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/54.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 2124691 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @   2124691 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   2124691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 94.csrng_err.5720220597545178278795760932840438720481650011443040352451452109206165379949
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/94.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 11652373 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @  11652373 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  11652373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 5 failures:
  • Test csrng_stress_all has 5 failures.

    • 4.csrng_stress_all.79640851312462040978856550752182321117170026159735906794461886154038220211598
      Line 154, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/4.csrng_stress_all/latest/run.log

        UVM_ERROR @ 306002894 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 306002894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 11.csrng_stress_all.109361300536310800207189656346040769654779884514754069783656634239099495095092
      Line 156, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/11.csrng_stress_all/latest/run.log

        UVM_ERROR @ 6593735499 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 6593735499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,514): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:
  • Test csrng_intr has 1 failures.

    • 2.csrng_intr.9364550267431726228718541486173354286647647453458002480059378634607990182572
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,514): (time 86737567 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
        UVM_ERROR @  86737567 ps: (csrng_cmd_stage.sv:514) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
        UVM_INFO @  86737567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---