DMA Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	2.781ms	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	1.637ms	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	1.381ms	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	60.720us	5	5	100.00
V1	csr_rw	dma_csr_rw	2.000s	16.121us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	13.000s	6.416ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	8.000s	165.757us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	110.088us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	16.121us	20	20	100.00
		dma_csr_aliasing	8.000s	165.757us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.900m	7.565ms	5	5	100.00
V2	dma_memory_tl_error	dma_memory_stress	12.283m	215.789ms	3	3	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	8.300m	245.928ms	3	3	100.00
V2	dma_handshake_stress	dma_handshake_stress	8.300m	245.928ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	12.283m	215.789ms	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	15.800m	284.514ms	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	8.300m	245.928ms	3	3	100.00
V2	dma_abort	dma_abort	20.000s	1.674ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	2.983m	25.974ms	3	3	100.00
V2	alert_test	dma_alert_test	7.000s	34.588us	50	50	100.00
V2	intr_test	dma_intr_test	2.000s	26.379us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	4.000s	136.102us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	4.000s	136.102us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	60.720us	5	5	100.00
		dma_csr_rw	2.000s	16.121us	20	20	100.00
		dma_csr_aliasing	8.000s	165.757us	5	5	100.00
		dma_same_csr_outstanding	3.000s	111.841us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	60.720us	5	5	100.00
		dma_csr_rw	2.000s	16.121us	20	20	100.00
		dma_csr_aliasing	8.000s	165.757us	5	5	100.00
		dma_same_csr_outstanding	3.000s	111.841us	20	20	100.00
V2		TOTAL			164	164	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	22.000s	96.527us	5	5	100.00
		dma_generic_stress	15.800m	284.514ms	5	5	100.00
		dma_handshake_stress	8.300m	245.928ms	3	3	100.00
V2S	dma_config_lock	dma_config_lock	9.000s	567.137us	15	15	100.00
V2S	tl_intg_err	dma_tl_intg_err	4.000s	704.680us	20	20	100.00
		dma_sec_cm	2.000s	12.075us	5	5	100.00
V2S		TOTAL			45	45	100.00
	Unmapped tests	dma_short_transfer	2.417m	14.748ms	24	25	96.00
		dma_longer_transfer	13.000s	1.324ms	5	5	100.00
		dma_stress_all_with_rand_reset	9.000s	1.018ms	0	1	0.00
		TOTAL			393	395	99.49

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.25	97.38	95.83	96.89	96.04	77.37	92.96	95.97	77.09

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.2811407783363256806880728813149808446822382047855730012320929925645493427905
      Line 104, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1018079185ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1018079185ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ *ps: (dma_pull_seq.sv:92) [seq_host] Check failed fifo_intr_clear_reg[a_addr] == rsp.a_data (* [*] vs * [*]) Invalid FIFO reg value detected has 1 failures:

  • Test dma_short_transfer has 1 failures.

    • 11.dma_short_transfer.83919480789862412779262706376934736768087338177983898382699603781109980583553
      Line 1932, in log /nightly/current_run/scratch/master/dma-sim-xcelium/11.dma_short_transfer/latest/run.log

        UVM_ERROR @ 20536624349ps: (dma_pull_seq.sv:92) [uvm_test_top.env.tl_agent_dma_host.sequencer.seq_host] Check failed fifo_intr_clear_reg[a_addr] == rsp.a_data (2465610558 [0x92f63b3e] vs 3419130827 [0xcbcbcbcb]) Invalid FIFO reg value detected
        UVM_INFO @ 20536624349ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---