EDN Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.350s 16.890us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.870s 17.068us 5 5 100.00
V1 csr_rw edn_csr_rw 1.060s 15.549us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.490s 461.645us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.480s 39.296us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.610s 112.757us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.060s 15.549us 20 20 100.00
edn_csr_aliasing 1.480s 39.296us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.155m 4.392ms 300 300 100.00
V2 csrng_commands edn_genbits 1.155m 4.392ms 300 300 100.00
V2 genbits edn_genbits 1.155m 4.392ms 300 300 100.00
V2 interrupts edn_intr 1.490s 20.927us 50 50 100.00
V2 alerts edn_alert 1.660s 27.577us 200 200 100.00
V2 errs edn_err 1.700s 24.407us 100 100 100.00
V2 disable edn_disable 1.310s 13.585us 50 50 100.00
edn_disable_auto_req_mode 1.700s 42.763us 50 50 100.00
V2 stress_all edn_stress_all 7.500s 550.967us 50 50 100.00
V2 intr_test edn_intr_test 0.990s 13.059us 50 50 100.00
V2 alert_test edn_alert_test 1.450s 42.697us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.010s 505.928us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.010s 505.928us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.870s 17.068us 5 5 100.00
edn_csr_rw 1.060s 15.549us 20 20 100.00
edn_csr_aliasing 1.480s 39.296us 5 5 100.00
edn_same_csr_outstanding 1.400s 64.800us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.870s 17.068us 5 5 100.00
edn_csr_rw 1.060s 15.549us 20 20 100.00
edn_csr_aliasing 1.480s 39.296us 5 5 100.00
edn_same_csr_outstanding 1.400s 64.800us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.390s 2.025ms 5 5 100.00
edn_tl_intg_err 3.140s 374.428us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.270s 40.686us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.660s 27.577us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.390s 2.025ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.390s 2.025ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.390s 2.025ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.390s 2.025ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.660s 27.577us 200 200 100.00
edn_sec_cm 9.390s 2.025ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.660s 27.577us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.140s 374.428us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.136m 7.311ms 37 50 74.00
V3 TOTAL 37 50 74.00
TOTAL 1117 1130 98.85

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.80 98.87 94.29 97.02 93.60 96.33 97.56 92.94

Failure Buckets