ENTROPY_SRC/RNG_16BITS Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 3.000s 46.182us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 31.000s 48.189us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 31.000s 72.597us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 24.000s 594.834us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 15.000s 289.930us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 125.423us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 31.000s 72.597us 20 20 100.00
entropy_src_csr_aliasing 15.000s 289.930us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 3.000s 46.182us 50 50 100.00
entropy_src_rng 14.233m 19.082ms 300 300 100.00
entropy_src_fw_ov 14.783m 20.051ms 299 300 99.67
V2 firmware_mode entropy_src_fw_ov 14.783m 20.051ms 299 300 99.67
V2 rng_mode entropy_src_rng 14.233m 19.082ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 22.033m 20.075ms 388 400 97.00
V2 health_checks entropy_src_rng 14.233m 19.082ms 300 300 100.00
V2 conditioning entropy_src_rng 14.233m 19.082ms 300 300 100.00
V2 interrupts entropy_src_rng 14.233m 19.082ms 300 300 100.00
entropy_src_intr 1.017m 9.629ms 50 50 100.00
V2 alerts entropy_src_rng 14.233m 19.082ms 300 300 100.00
entropy_src_functional_alerts 11.000s 208.180us 50 50 100.00
V2 stress_all entropy_src_stress_all 11.433m 16.176ms 49 50 98.00
V2 functional_errors entropy_src_functional_errors 11.083m 10.008ms 992 1000 99.20
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 1.333m 1.307ms 47 50 94.00
V2 intr_test entropy_src_intr_test 31.000s 84.670us 50 50 100.00
V2 alert_test entropy_src_alert_test 3.000s 30.737us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 36.000s 229.348us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 36.000s 229.348us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 31.000s 48.189us 5 5 100.00
entropy_src_csr_rw 31.000s 72.597us 20 20 100.00
entropy_src_csr_aliasing 15.000s 289.930us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 266.368us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 31.000s 48.189us 5 5 100.00
entropy_src_csr_rw 31.000s 72.597us 20 20 100.00
entropy_src_csr_aliasing 15.000s 289.930us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 266.368us 20 20 100.00
V2 TOTAL 2315 2340 98.93
V2S tl_intg_err entropy_src_sec_cm 6.000s 585.205us 5 5 100.00
entropy_src_tl_intg_err 33.000s 315.371us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 14.233m 19.082ms 300 300 100.00
entropy_src_cfg_regwen 3.000s 82.836us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 14.233m 19.082ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 14.233m 19.082ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 14.233m 19.082ms 300 300 100.00
entropy_src_fw_ov 14.783m 20.051ms 299 300 99.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 11.083m 10.008ms 992 1000 99.20
entropy_src_sec_cm 6.000s 585.205us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 11.083m 10.008ms 992 1000 99.20
entropy_src_sec_cm 6.000s 585.205us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 14.233m 19.082ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 11.083m 10.008ms 992 1000 99.20
entropy_src_sec_cm 6.000s 585.205us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 11.083m 10.008ms 992 1000 99.20
entropy_src_sec_cm 6.000s 585.205us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 11.083m 10.008ms 992 1000 99.20
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 11.000s 208.180us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 33.000s 315.371us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 13.283m 20.072ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 2545 2570 99.03

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
85.51 96.16 90.52 98.73 92.35 57.85 97.92 89.50 93.64

Failure Buckets