HMAC Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.410s	2.721ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.330s	35.382us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.270s	125.970us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.810s	6.293ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	5.550s	134.736us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	10.350m	170.048ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.270s	125.970us	20	20	100.00
		hmac_csr_aliasing	5.550s	134.736us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.321m	6.898ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.544m	1.474ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.635m	7.330ms	30	30	100.00
		hmac_test_sha384_vectors	8.809m	15.559ms	75	75	100.00
		hmac_test_sha512_vectors	8.655m	54.901ms	75	75	100.00
		hmac_test_hmac256_vectors	14.710s	638.613us	50	50	100.00
		hmac_test_hmac384_vectors	15.760s	3.592ms	60	60	100.00
		hmac_test_hmac512_vectors	19.220s	378.966us	75	75	100.00
V2	burst_wr	hmac_burst_wr	32.990s	620.158us	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	22.967m	7.484ms	10	10	100.00
V2	error	hmac_error	1.595m	2.080ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.682m	2.419ms	10	10	100.00
V2	save_and_restore	hmac_smoke	16.410s	2.721ms	10	10	100.00
		hmac_long_msg	1.321m	6.898ms	10	10	100.00
		hmac_back_pressure	1.544m	1.474ms	25	25	100.00
		hmac_datapath_stress	22.967m	7.484ms	10	10	100.00
		hmac_burst_wr	32.990s	620.158us	50	50	100.00
		hmac_stress_all	33.310m	14.185ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.410s	2.721ms	10	10	100.00
		hmac_long_msg	1.321m	6.898ms	10	10	100.00
		hmac_back_pressure	1.544m	1.474ms	25	25	100.00
		hmac_datapath_stress	22.967m	7.484ms	10	10	100.00
		hmac_wipe_secret	1.682m	2.419ms	10	10	100.00
		hmac_test_sha256_vectors	4.635m	7.330ms	30	30	100.00
		hmac_test_sha384_vectors	8.809m	15.559ms	75	75	100.00
		hmac_test_sha512_vectors	8.655m	54.901ms	75	75	100.00
		hmac_test_hmac256_vectors	14.710s	638.613us	50	50	100.00
		hmac_test_hmac384_vectors	15.760s	3.592ms	60	60	100.00
		hmac_test_hmac512_vectors	19.220s	378.966us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.410s	2.721ms	10	10	100.00
		hmac_long_msg	1.321m	6.898ms	10	10	100.00
		hmac_back_pressure	1.544m	1.474ms	25	25	100.00
		hmac_datapath_stress	22.967m	7.484ms	10	10	100.00
		hmac_burst_wr	32.990s	620.158us	50	50	100.00
		hmac_error	1.595m	2.080ms	10	10	100.00
		hmac_wipe_secret	1.682m	2.419ms	10	10	100.00
		hmac_test_sha256_vectors	4.635m	7.330ms	30	30	100.00
		hmac_test_sha384_vectors	8.809m	15.559ms	75	75	100.00
		hmac_test_sha512_vectors	8.655m	54.901ms	75	75	100.00
		hmac_test_hmac256_vectors	14.710s	638.613us	50	50	100.00
		hmac_test_hmac384_vectors	15.760s	3.592ms	60	60	100.00
		hmac_test_hmac512_vectors	19.220s	378.966us	75	75	100.00
		hmac_stress_all	33.310m	14.185ms	50	50	100.00
V2	stress_all	hmac_stress_all	33.310m	14.185ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.930s	24.798us	50	50	100.00
V2	intr_test	hmac_intr_test	0.960s	16.994us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.330s	445.841us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.330s	445.841us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.330s	35.382us	5	5	100.00
		hmac_csr_rw	1.270s	125.970us	20	20	100.00
		hmac_csr_aliasing	5.550s	134.736us	5	5	100.00
		hmac_same_csr_outstanding	2.590s	300.360us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.330s	35.382us	5	5	100.00
		hmac_csr_rw	1.270s	125.970us	20	20	100.00
		hmac_csr_aliasing	5.550s	134.736us	5	5	100.00
		hmac_same_csr_outstanding	2.590s	300.360us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.460s	102.099us	5	5	100.00
		hmac_tl_intg_err	4.840s	448.114us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.840s	448.114us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.410s	2.721ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	6.850s	137.645us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	7.985m	54.801ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	1.320s	14.269us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.95	96.74	100.00	100.00	99.83	97.14	100.00