I2C Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.482m	2.358ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	36.290s	13.187ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.120s	27.721us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.070s	782.370us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.990s	732.111us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.740s	39.957us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.780s	412.673us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.070s	782.370us	20	20	100.00
		i2c_csr_aliasing	1.740s	39.957us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	7.070s	1.261ms	0	50	0.00
V2	host_stress_all	i2c_host_stress_all	53.339m	600.000ms	13	50	26.00
V2	host_maxperf	i2c_host_perf	25.429m	48.376ms	50	50	100.00
V2	host_override	i2c_host_override	1.100s	26.626us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.290m	9.690ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.628m	2.649ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.670s	225.468us	50	50	100.00
		i2c_host_fifo_fmt_empty	26.060s	1.171ms	50	50	100.00
		i2c_host_fifo_reset_rx	12.820s	900.605us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.857m	3.430ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	40.000s	1.199ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	5.670s	194.225us	16	50	32.00
V2	target_glitch	i2c_target_glitch	3.740s	1.866ms	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	21.564m	65.229ms	49	50	98.00
V2	target_maxperf	i2c_target_perf	7.030s	19.973ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.149m	10.168ms	50	50	100.00
		i2c_target_intr_smoke	9.000s	2.857ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.320s	287.531us	50	50	100.00
		i2c_target_fifo_reset_tx	2.470s	440.043us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	22.701m	68.527ms	50	50	100.00
		i2c_target_stress_rd	1.149m	10.168ms	50	50	100.00
		i2c_target_intr_stress_wr	9.713m	35.722ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.920s	4.641ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	2.938m	4.209ms	48	50	96.00
V2	bad_address	i2c_target_bad_addr	8.680s	1.615ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	48.890s	10.015ms	28	50	56.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	4.290s	10.844ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	2.150s	323.348us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	25.429m	48.376ms	50	50	100.00
		i2c_host_perf_precise	15.275m	23.224ms	49	50	98.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	40.000s	1.199ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	11.510s	652.795us	48	50	96.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	4.560s	1.282ms	50	50	100.00
		i2c_target_nack_acqfull_addr	4.080s	3.834ms	50	50	100.00
		i2c_target_nack_txstretch	2.280s	867.713us	36	50	72.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	21.990s	2.908ms	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.450s	2.191ms	50	50	100.00
V2	alert_test	i2c_alert_test	1.030s	17.857us	50	50	100.00
V2	intr_test	i2c_intr_test	1.100s	23.891us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.680s	57.214us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.680s	57.214us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.120s	27.721us	5	5	100.00
		i2c_csr_rw	2.070s	782.370us	20	20	100.00
		i2c_csr_aliasing	1.740s	39.957us	5	5	100.00
		i2c_same_csr_outstanding	1.560s	95.245us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.120s	27.721us	5	5	100.00
		i2c_csr_rw	2.070s	782.370us	20	20	100.00
		i2c_csr_aliasing	1.740s	39.957us	5	5	100.00
		i2c_same_csr_outstanding	1.560s	95.245us	20	20	100.00
V2		TOTAL			1627	1792	90.79
V2S	tl_intg_err	i2c_tl_intg_err	2.610s	451.625us	20	20	100.00
		i2c_sec_cm	1.370s	245.553us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.610s	451.625us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	1.235m	2.181ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.480s	437.184us	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	28.460s	856.865us	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1807	2042	88.49

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.65	97.13	88.58	74.17	46.43	93.54	96.41	89.32

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 96 failures:

Test i2c_host_error_intr has 50 failures.

0.i2c_host_error_intr.17843898673210673837541241399745412307015067621828817513045527949866010007263
Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 119555593 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 119555593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_error_intr.75907104055968126080502224341787849159820808946669690295961252737120801452304
Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 141443366 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 141443366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.

Test i2c_host_stress_all has 25 failures.

1.i2c_host_stress_all.95386052189557900359503428892091876150743657491233981913913385977845952342915
Line 144, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 40849405483 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 40849405483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_host_stress_all.35724937994788630994841318303524052808148454671683853548678648725832649567015
Line 111, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 28398238719 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 28398238719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 23 more failures.

Test i2c_target_stress_all_with_rand_reset has 6 failures.

2.i2c_target_stress_all_with_rand_reset.107558839596008103145909962519120114539344389844002143985895075383173937023097
Line 90, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4942953361 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 4942953361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_target_stress_all_with_rand_reset.35070133414049143158448623224676911760155792940770352784633907780880341629326
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  19065618 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  19065618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test i2c_host_mode_toggle has 15 failures.

3.i2c_host_mode_toggle.92763375275572280586640094436669572035662629119187794523204954711359808426574
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  15400735 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  15400735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.i2c_host_mode_toggle.104382952105426664235490436755966688760164616087012845493501144243114719544900
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  49633301 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  49633301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 27 failures:
- Test i2c_target_unexp_stop has 27 failures.
  - 4.i2c_target_unexp_stop.5725019744023652020680343951415440306055211478289138863969540501214379255161
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 176422987 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 100 [0x64])
  UVM_INFO @ 176422987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.i2c_target_unexp_stop.26692277297843911049390412407854238148030854269433396615628943494158200121955
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 396419299 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 90 [0x5a])
  UVM_INFO @ 396419299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 25 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 22 failures:
- Test i2c_target_hrst has 22 failures.
  - 1.i2c_target_hrst.4121879416587081611493077384309758529239883971955324245215044198236270065086
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10691272827 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10691272827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.i2c_target_hrst.15269229344738217806312949905448504232189412582434060934628540412550359783185
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10263844498 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10263844498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 20 more failures.

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 15 failures:

Test i2c_host_stress_all has 8 failures.

0.i2c_host_stress_all.59660736370322405430744629148344039441438081264004080929515681677925018570823
Line 132, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 63803722622 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4035309

4.i2c_host_stress_all.103178339748503576030803178136461261651273055996956685454564035673651701561599
Line 134, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 17238777622 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @21387241

... and 6 more failures.

Test i2c_host_mode_toggle has 7 failures.

6.i2c_host_mode_toggle.34595115828513352885637034239433484892598866930300855293660993757497428709027
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 242093026 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @115680

10.i2c_host_mode_toggle.86454713650806213524416292284566461343983094218155059460955406343655317741264
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 317309672 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @35622

... and 5 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
- Test i2c_target_nack_txstretch has 14 failures.
  - 0.i2c_target_nack_txstretch.7846107647220329877697176379600465178900810146994988369056411004141489215941
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 867712522 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 867712522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.i2c_target_nack_txstretch.73240722995234159770020506026877892837437314220638273993526168672308390952721
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 569924634 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 569924634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.

UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.103767202630868515337579480576338062445221202049443164923132455984970688496307
Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3605571064 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3605571064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.64027934691349999480560466790292506694062587686098986262288368457561490863404
Line 87, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4780113127 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4780113127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 3 failures.

1.i2c_target_stress_all_with_rand_reset.21976892791366087472403827156173817484170760724547076684088552228459100249320
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1122473195 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1122473195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.65377154732899252868515549583839698215091105191721357375095615407764496377173
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 373999500 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 373999500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 12 failures:
- Test i2c_target_unexp_stop has 12 failures.
  - 1.i2c_target_unexp_stop.55129263947292781240129984998898929658712003412125399206448043133920199189186
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 304236906 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 304236906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_unexp_stop.109634931746771488981703904044824478385828550935928827269668935375811553218960
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 679148384 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 679148384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 11 failures:

Test i2c_target_unexp_stop has 11 failures.

0.i2c_target_unexp_stop.99278259632544024402196562155345246385814603914829198308650938968206254910374
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 973010403 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 973010403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_unexp_stop.55772352365281352382558303562377335663556917060391970823784153289359379904623
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 2171139376 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 2171139376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 10 failures:

Test i2c_host_mode_toggle has 9 failures.

4.i2c_host_mode_toggle.70808423564636157469467011472817853598611103698167417612496287701360419707411
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 159436891 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

8.i2c_host_mode_toggle.65163204995833433835383778834155209746125340476895045975702368242823201932519
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 459499448 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 7 more failures.

Test i2c_host_perf_precise has 1 failures.

8.i2c_host_perf_precise.31656749994458193238574269602046443578966356275640065400172081873094897545245
Line 79, in log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_host_perf_precise/latest/run.log

  UVM_ERROR @ 6999888787 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:

Test i2c_host_stress_all has 3 failures.

2.i2c_host_stress_all.112938830364098335815715008237672906291960329794945802351614382094960387199956
Line 149, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 101872380452 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @17442655

7.i2c_host_stress_all.47645328254747199279185107544042001341819049267181073386584846514269224916393
Line 141, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 92904530604 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @24903485

... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
- Test i2c_host_mode_toggle has 3 failures.
  - 11.i2c_host_mode_toggle.34783942575449611642907553901771858486171741787732857635946784547705939875547
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  94891103 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x2d381714, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  94891103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 23.i2c_host_mode_toggle.29272449236312388621134056289152933620381894928698856738877097067299546849750
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/23.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  40709418 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xd3234594, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  40709418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.65638251747691478572267189363797465232743986088760443315180262351446225512809
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 1865545844 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 1865545844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.106531036506731270797767691013152563916828552292457600389399061985738530189462
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 3993489357 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 3993489357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
- Test i2c_target_tx_stretch_ctrl has 2 failures.
  - 12.i2c_target_tx_stretch_ctrl.10427671949847376310242389516995350381058149880013594398127986689805716788648
    Line 127, in log /nightly/current_run/scratch/master/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 24.i2c_target_tx_stretch_ctrl.88001033173425311487692243677879746540177942031821248313696539447155405031107
    Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/24.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 2 failures:
- Test i2c_target_stretch has 2 failures.
  - 22.i2c_target_stretch.20242182667734473864409114879238635121036804272793691533835990029984579932082
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/22.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10004965737 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10004965737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 46.i2c_target_stretch.54333684576332094607957694512933500672411493960901627028463922793077711664956
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/46.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10047461238 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10047461238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.1353820526543492141801127602020776690406385109596647587689469554382718065155
    Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 473802198 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 473802198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
- Test i2c_target_stress_all has 1 failures.
  - 20.i2c_target_stress_all.106718654334865844931075911589362409322598647167888270546120103134547725077483
    Line 94, in log /nightly/current_run/scratch/master/i2c-sim-vcs/20.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 65228710695 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 65228710695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 38.i2c_host_stress_all.60665082475873438185795085735841318618119780034324705709656347812748925975727
    Line 103, in log /nightly/current_run/scratch/master/i2c-sim-vcs/38.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```