KEYMGR Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: `7302728`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	46.960s	14.495ms	50	50	100.00
V1	random	keymgr_random	1.145m	9.037ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.380s	19.129us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.730s	59.334us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	20.870s	7.807ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	7.810s	301.838us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.400s	50.908us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.730s	59.334us	20	20	100.00
		keymgr_csr_aliasing	7.810s	301.838us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.352m	2.713ms	50	50	100.00
V2	sideload	keymgr_sideload	29.670s	1.620ms	49	50	98.00
		keymgr_sideload_kmac	29.410s	6.117ms	50	50	100.00
		keymgr_sideload_aes	40.570s	10.504ms	49	50	98.00
		keymgr_sideload_otbn	32.780s	6.545ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	15.490s	2.010ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	6.910s	706.818us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	20.470s	8.376ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	41.810s	9.404ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	11.840s	1.684ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	20.660s	2.252ms	50	50	100.00
V2	stress_all	keymgr_stress_all	6.793m	17.976ms	46	50	92.00
V2	intr_test	keymgr_intr_test	1.250s	27.929us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.260s	37.211us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	6.150s	1.335ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	6.150s	1.335ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.380s	19.129us	5	5	100.00
		keymgr_csr_rw	1.730s	59.334us	20	20	100.00
		keymgr_csr_aliasing	7.810s	301.838us	5	5	100.00
		keymgr_same_csr_outstanding	4.650s	253.109us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.380s	19.129us	5	5	100.00
		keymgr_csr_rw	1.730s	59.334us	20	20	100.00
		keymgr_csr_aliasing	7.810s	301.838us	5	5	100.00
		keymgr_same_csr_outstanding	4.650s	253.109us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	sec_cm_additional_check	keymgr_sec_cm	14.230s	1.284ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	14.230s	1.284ms	5	5	100.00
		keymgr_tl_intg_err	11.890s	2.275ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.130s	661.017us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.130s	661.017us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.130s	661.017us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.130s	661.017us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.950s	2.252ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	14.230s	1.284ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	14.230s	1.284ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	11.890s	2.275ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.130s	661.017us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.352m	2.713ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.145m	9.037ms	50	50	100.00
		keymgr_csr_rw	1.730s	59.334us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.145m	9.037ms	50	50	100.00
		keymgr_csr_rw	1.730s	59.334us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.145m	9.037ms	50	50	100.00
		keymgr_csr_rw	1.730s	59.334us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	6.910s	706.818us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	11.840s	1.684ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	11.840s	1.684ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.145m	9.037ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	16.940s	2.156ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	14.230s	1.284ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	14.230s	1.284ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	14.230s	1.284ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	43.520s	6.095ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	6.910s	706.818us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	14.230s	1.284ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	14.230s	1.284ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	14.230s	1.284ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	43.520s	6.095ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	43.520s	6.095ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	14.230s	1.284ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	43.520s	6.095ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	14.230s	1.284ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	43.520s	6.095ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	22.600s	3.680ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1084	1110	97.66

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.69	99.13	97.99	98.72	100.00	99.01	97.71	91.23

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
- Test keymgr_stress_all_with_rand_reset has 18 failures.
  - 1.keymgr_stress_all_with_rand_reset.42934638429748616084779699097316441381605124087598523702669029043925734184490
    Line 232, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 230092726 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 230092726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.keymgr_stress_all_with_rand_reset.101880706716757065832888112118129041971368085580263367083556140284081113379763
    Line 396, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 560123487 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 560123487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.

UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 5 failures:

Test keymgr_sideload has 1 failures.

15.keymgr_sideload.69475360863663634262969351312967017582806575470317027289425412725352986970269
Line 106, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/15.keymgr_sideload/latest/run.log

  UVM_ERROR @  31421590 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  31421590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sideload_aes has 1 failures.

16.keymgr_sideload_aes.101599050966650429019648851222833451280465914480014556698968396232445770669166
Line 114, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/16.keymgr_sideload_aes/latest/run.log

  UVM_ERROR @  13504359 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  13504359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 3 failures.

21.keymgr_stress_all.36400038406573387680414707916328367480629824236540328748740036586660991502953
Line 984, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/21.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 121370723 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 121370723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.keymgr_stress_all.68015453242909819107336012073732716948584886359291822485356039556702194566801
Line 2683, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/38.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 1089162036 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 1089162036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:1142) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 23.keymgr_stress_all_with_rand_reset.89810695996698805543398537900583925562342448614066678388761234025260237646057
    Line 113, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/23.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 746938548 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 746938548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Sealing Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

25.keymgr_lc_disable.106146608914510461280238228694142211214629320577224662543997799658006617299571
Line 431, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/25.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 146968907 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (7317156997671989141164420279460545977032396791470032291299482122906841491867565579144498658072254860279793695539201976311292566916926760730951171525792484 [0x8bb584b4c63d36528bf70e951e39d60b23914fc2e33c11d0e511784e078d0b4dce6a87809da250ca82312c78b5a02664284789d2c75edc04eccf580ffa9352e4] vs 7317156997671989141164420279460545977032396791470032291299482122906841491867565579144498658072254860279793695539201976311292566916926760730951171525792484 [0x8bb584b4c63d36528bf70e951e39d60b23914fc2e33c11d0e511784e078d0b4dce6a87809da250ca82312c78b5a02664284789d2c75edc04eccf580ffa9352e4]) AES key at state StDisabled for Sealing Aes
  UVM_INFO @ 146968907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 39.keymgr_stress_all.29772389054020916182045828097690128184555868470945581395741631253349819669390
    Line 635, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/39.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 812797081 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_4
  UVM_INFO @ 812797081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```