KEYMGR_DPE Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	6.528m	21.016ms	50	50	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.660s	46.767us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.420s	102.450us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	8.970s	860.207us	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	4.210s	84.285us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	2.160s	60.854us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.420s	102.450us	20	20	100.00
		keymgr_dpe_csr_aliasing	4.210s	84.285us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	intr_test	keymgr_dpe_intr_test	1.060s	16.644us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	1.320s	32.709us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	3.540s	466.158us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	3.540s	466.158us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.660s	46.767us	5	5	100.00
		keymgr_dpe_csr_rw	1.420s	102.450us	20	20	100.00
		keymgr_dpe_csr_aliasing	4.210s	84.285us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.620s	553.582us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.660s	46.767us	5	5	100.00
		keymgr_dpe_csr_rw	1.420s	102.450us	20	20	100.00
		keymgr_dpe_csr_aliasing	4.210s	84.285us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.620s	553.582us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	11.570s	2.285ms	5	5	100.00
		keymgr_dpe_tl_intg_err	6.460s	576.315us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	2.460s	272.023us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	2.460s	272.023us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	2.460s	272.023us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	2.460s	272.023us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	6.460s	1.594ms	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	11.570s	2.285ms	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	11.570s	2.285ms	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			310	310	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.61	97.62	90.35	63.15	75.68	94.61	97.62	17.25