KMAC/MASKED Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.817m	14.260ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.120s	166.229us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.260s	72.466us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.070s	6.842ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.820s	2.009ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.130s	1.471ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.260s	72.466us	20	20	100.00
		kmac_csr_aliasing	6.820s	2.009ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.810s	76.775us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.240s	44.956us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.021h	136.585ms	50	50	100.00
V2	burst_write	kmac_burst_write	21.349m	38.130ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.776m	81.487ms	5	5	100.00
		kmac_test_vectors_sha3_256	34.948m	355.332ms	5	5	100.00
		kmac_test_vectors_sha3_384	27.510m	282.787ms	5	5	100.00
		kmac_test_vectors_sha3_512	19.068m	65.748ms	5	5	100.00
		kmac_test_vectors_shake_128	37.902m	1.738s	5	5	100.00
		kmac_test_vectors_shake_256	30.008m	159.315ms	5	5	100.00
		kmac_test_vectors_kmac	3.480s	85.352us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.260s	116.287us	5	5	100.00
V2	sideload	kmac_sideload	7.707m	6.348ms	50	50	100.00
V2	app	kmac_app	6.596m	110.884ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.425m	58.555ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.464m	16.284ms	50	50	100.00
V2	error	kmac_error	7.740m	23.553ms	50	50	100.00
V2	key_error	kmac_key_error	17.180s	8.107ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	9.010s	251.338us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	34.580s	5.801ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.170s	5.569ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.166m	7.612ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	27.010s	2.954ms	50	50	100.00
V2	stress_all	kmac_stress_all	55.690m	1.090s	49	50	98.00
V2	intr_test	kmac_intr_test	1.020s	22.747us	50	50	100.00
V2	alert_test	kmac_alert_test	1.290s	21.747us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.170s	184.560us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.170s	184.560us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.120s	166.229us	5	5	100.00
		kmac_csr_rw	1.260s	72.466us	20	20	100.00
		kmac_csr_aliasing	6.820s	2.009ms	5	5	100.00
		kmac_same_csr_outstanding	2.050s	223.977us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.120s	166.229us	5	5	100.00
		kmac_csr_rw	1.260s	72.466us	20	20	100.00
		kmac_csr_aliasing	6.820s	2.009ms	5	5	100.00
		kmac_same_csr_outstanding	2.050s	223.977us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.800s	222.237us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.800s	222.237us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.800s	222.237us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.800s	222.237us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.820s	947.186us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.852m	14.090ms	5	5	100.00
		kmac_tl_intg_err	3.830s	248.244us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.830s	248.244us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	27.010s	2.954ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.817m	14.260ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.707m	6.348ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.800s	222.237us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.852m	14.090ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.852m	14.090ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.852m	14.090ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.817m	14.260ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	27.010s	2.954ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.852m	14.090ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.161m	75.060ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.817m	14.260ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.283m	1.916ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			937	940	99.68

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.35	99.27	94.45	99.89	80.99	97.15	97.83	97.86

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.entropy_period.prescaler reset value: * has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 3.kmac_shadow_reg_errors_with_csr_rw.81678419813419170476230830260996195359784341548733537557246654368315158235
      Line 416, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  75053247 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (645 [0x285] vs 565 [0x235]) Regname: kmac_reg_block.entropy_period.prescaler reset value: 0x0
        UVM_INFO @  75053247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 6.kmac_stress_all_with_rand_reset.34663551881338356239203436825127504135763993755832196158757108855559599942191
      Line 357, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4450161586 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 4450161586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_stress_all has 1 failures.

    • 19.kmac_stress_all.30529342073192358194674033857987508935972958523670509370629637115169585354995
      Line 120, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_stress_all/latest/run.log

        UVM_ERROR @ 38995997689 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @ 38995997689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---