KMAC/UNMASKED Simulation Results

Friday October 03 2025 17:09:52 UTC

GitHub Revision: 7302728

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.042m	11.038ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.440s	50.087us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.500s	27.635us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.980s	18.026ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.650s	538.102us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.210s	503.292us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.500s	27.635us	20	20	100.00
		kmac_csr_aliasing	10.650s	538.102us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.110s	137.187us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.860s	40.623us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	53.910m	348.527ms	50	50	100.00
V2	burst_write	kmac_burst_write	16.672m	190.340ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.256m	62.057ms	5	5	100.00
		kmac_test_vectors_sha3_256	22.421m	50.235ms	5	5	100.00
		kmac_test_vectors_sha3_384	20.510m	248.120ms	5	5	100.00
		kmac_test_vectors_sha3_512	10.932m	18.268ms	5	5	100.00
		kmac_test_vectors_shake_128	37.083m	107.817ms	5	5	100.00
		kmac_test_vectors_shake_256	29.217m	107.107ms	5	5	100.00
		kmac_test_vectors_kmac	2.590s	35.238us	5	5	100.00
		kmac_test_vectors_kmac_xof	2.710s	116.722us	5	5	100.00
V2	sideload	kmac_sideload	6.239m	182.919ms	50	50	100.00
V2	app	kmac_app	6.324m	65.963ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.421m	182.536ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.458m	20.197ms	50	50	100.00
V2	error	kmac_error	6.546m	53.978ms	50	50	100.00
V2	key_error	kmac_key_error	17.470s	11.262ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.145m	10.124ms	35	50	70.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.610s	7.986ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	33.710s	3.894ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.354m	63.550ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	43.970s	1.979ms	50	50	100.00
V2	stress_all	kmac_stress_all	56.134m	159.210ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.190s	153.041us	50	50	100.00
V2	alert_test	kmac_alert_test	1.270s	39.968us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.990s	146.291us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.990s	146.291us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.440s	50.087us	5	5	100.00
		kmac_csr_rw	1.500s	27.635us	20	20	100.00
		kmac_csr_aliasing	10.650s	538.102us	5	5	100.00
		kmac_same_csr_outstanding	2.850s	112.640us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.440s	50.087us	5	5	100.00
		kmac_csr_rw	1.500s	27.635us	20	20	100.00
		kmac_csr_aliasing	10.650s	538.102us	5	5	100.00
		kmac_same_csr_outstanding	2.850s	112.640us	20	20	100.00
V2		TOTAL			725	740	97.97
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.250s	193.437us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.250s	193.437us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.250s	193.437us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.250s	193.437us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.540s	426.250us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.355m	6.155ms	5	5	100.00
		kmac_tl_intg_err	5.570s	254.133us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.570s	254.133us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	43.970s	1.979ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.042m	11.038ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.239m	182.919ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.250s	193.437us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.355m	6.155ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.355m	6.155ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.355m	6.155ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.042m	11.038ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	43.970s	1.979ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.355m	6.155ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.994m	36.915ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.042m	11.038ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.423m	25.006ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			923	940	98.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.66	97.69	94.37	100.00	73.55	96.04	97.74	96.26

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 5 failures:

  • Test kmac_sideload_invalid has 5 failures.

    • 18.kmac_sideload_invalid.83189124517210646615033671132358748306275849240121056082491104777994890320611
      Line 77, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10058619205 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbdcc1000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
        UVM_INFO @ 10058619205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 24.kmac_sideload_invalid.70418012524339015775998073099744234322945016768902765206117203793231893040676
      Line 77, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/24.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10064396629 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x84d3b000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
        UVM_INFO @ 10064396629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 3 failures:

  • Test kmac_sideload_invalid has 3 failures.

    • 20.kmac_sideload_invalid.49934126551746302997151088136601856056326701759204432832349558582263653497389
      Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/20.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10425544301 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf5d6b000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
        UVM_INFO @ 10425544301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 23.kmac_sideload_invalid.92929970185671302992669756042113349672318667314578279095502388641318789479665
      Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10029555105 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x92b20000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
        UVM_INFO @ 10029555105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 13.kmac_sideload_invalid.106443259747131059940697986977828670414755074845678254949896140702881245150642
      Line 92, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/13.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10182825067 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x44d26000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
        UVM_INFO @ 10182825067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 21.kmac_sideload_invalid.23859657498277276883171734810774483999885569786300450459538071969304864494839
      Line 92, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/21.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10124189623 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x40f26000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
        UVM_INFO @ 10124189623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 25.kmac_sideload_invalid.17873056662660038710815491547148556493898805789109132397641740012226376976840
      Line 81, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/25.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10040070874 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf70f1000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10040070874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 29.kmac_sideload_invalid.4519380164838155677451063673047353960264618938169986238421800886509446998338
      Line 80, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/29.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10244275189 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe9883000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10244275189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1142) [kmac_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.14036588226179270604028025484284132378471148228834507391872798112671806752204
      Line 221, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1035346817 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1035346817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=33) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 3.kmac_sideload_invalid.90882463371847943936456941485815953841082263580746652689490232868252415534158
      Line 108, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/3.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10199844617 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2b5f8000, Comparison=CompareOpEq, exp_data=0x1, call_count=33)
        UVM_INFO @ 10199844617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 5.kmac_stress_all_with_rand_reset.14284899087772859256867795792960783894148797207479696993340258675180257475574
      Line 191, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7246035872 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7246035872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 45.kmac_sideload_invalid.38178412621820972430586274162085420572201444117600362132167193937963832879025
      Line 94, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/45.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10173978688 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xaef26000, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
        UVM_INFO @ 10173978688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 48.kmac_sideload_invalid.80686519778644513603092912155330065517661642840319195443070720870255775000495
      Line 85, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/48.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10074315213 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x379d5000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
        UVM_INFO @ 10074315213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---